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586 lines
15 KiB
586 lines
15 KiB
/*
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* Copyright (C) STMicroelectronics SA 2015
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* Authors: Yannick Fertre <yannick.fertre@st.com>
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* Hugues Fruchet <hugues.fruchet@st.com>
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#ifdef CONFIG_VIDEO_STI_HVA_DEBUGFS
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#include <linux/seq_file.h>
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#endif
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#include "hva.h"
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#include "hva-hw.h"
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/* HVA register offsets */
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#define HVA_HIF_REG_RST 0x0100U
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#define HVA_HIF_REG_RST_ACK 0x0104U
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#define HVA_HIF_REG_MIF_CFG 0x0108U
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#define HVA_HIF_REG_HEC_MIF_CFG 0x010CU
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#define HVA_HIF_REG_CFL 0x0110U
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#define HVA_HIF_FIFO_CMD 0x0114U
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#define HVA_HIF_FIFO_STS 0x0118U
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#define HVA_HIF_REG_SFL 0x011CU
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#define HVA_HIF_REG_IT_ACK 0x0120U
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#define HVA_HIF_REG_ERR_IT_ACK 0x0124U
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#define HVA_HIF_REG_LMI_ERR 0x0128U
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#define HVA_HIF_REG_EMI_ERR 0x012CU
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#define HVA_HIF_REG_HEC_MIF_ERR 0x0130U
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#define HVA_HIF_REG_HEC_STS 0x0134U
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#define HVA_HIF_REG_HVC_STS 0x0138U
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#define HVA_HIF_REG_HJE_STS 0x013CU
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#define HVA_HIF_REG_CNT 0x0140U
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#define HVA_HIF_REG_HEC_CHKSYN_DIS 0x0144U
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#define HVA_HIF_REG_CLK_GATING 0x0148U
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#define HVA_HIF_REG_VERSION 0x014CU
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#define HVA_HIF_REG_BSM 0x0150U
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/* define value for version id register (HVA_HIF_REG_VERSION) */
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#define VERSION_ID_MASK 0x0000FFFF
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/* define values for BSM register (HVA_HIF_REG_BSM) */
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#define BSM_CFG_VAL1 0x0003F000
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#define BSM_CFG_VAL2 0x003F0000
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/* define values for memory interface register (HVA_HIF_REG_MIF_CFG) */
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#define MIF_CFG_VAL1 0x04460446
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#define MIF_CFG_VAL2 0x04460806
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#define MIF_CFG_VAL3 0x00000000
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/* define value for HEC memory interface register (HVA_HIF_REG_MIF_CFG) */
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#define HEC_MIF_CFG_VAL 0x000000C4
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/* Bits definition for clock gating register (HVA_HIF_REG_CLK_GATING) */
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#define CLK_GATING_HVC BIT(0)
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#define CLK_GATING_HEC BIT(1)
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#define CLK_GATING_HJE BIT(2)
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/* fix hva clock rate */
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#define CLK_RATE 300000000
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/* fix delay for pmruntime */
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#define AUTOSUSPEND_DELAY_MS 3
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/*
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* hw encode error values
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* NO_ERROR: Success, Task OK
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* H264_BITSTREAM_OVERSIZE: VECH264 Bitstream size > bitstream buffer
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* H264_FRAME_SKIPPED: VECH264 Frame skipped (refers to CPB Buffer Size)
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* H264_SLICE_LIMIT_SIZE: VECH264 MB > slice limit size
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* H264_MAX_SLICE_NUMBER: VECH264 max slice number reached
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* H264_SLICE_READY: VECH264 Slice ready
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* TASK_LIST_FULL: HVA/FPC task list full
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(discard latest transform command)
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* UNKNOWN_COMMAND: Transform command not known by HVA/FPC
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* WRONG_CODEC_OR_RESOLUTION: Wrong Codec or Resolution Selection
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* NO_INT_COMPLETION: Time-out on interrupt completion
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* LMI_ERR: Local Memory Interface Error
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* EMI_ERR: External Memory Interface Error
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* HECMI_ERR: HEC Memory Interface Error
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*/
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enum hva_hw_error {
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NO_ERROR = 0x0,
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H264_BITSTREAM_OVERSIZE = 0x2,
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H264_FRAME_SKIPPED = 0x4,
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H264_SLICE_LIMIT_SIZE = 0x5,
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H264_MAX_SLICE_NUMBER = 0x7,
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H264_SLICE_READY = 0x8,
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TASK_LIST_FULL = 0xF0,
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UNKNOWN_COMMAND = 0xF1,
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WRONG_CODEC_OR_RESOLUTION = 0xF4,
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NO_INT_COMPLETION = 0x100,
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LMI_ERR = 0x101,
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EMI_ERR = 0x102,
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HECMI_ERR = 0x103,
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};
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static irqreturn_t hva_hw_its_interrupt(int irq, void *data)
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{
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struct hva_dev *hva = data;
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/* read status registers */
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hva->sts_reg = readl_relaxed(hva->regs + HVA_HIF_FIFO_STS);
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hva->sfl_reg = readl_relaxed(hva->regs + HVA_HIF_REG_SFL);
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/* acknowledge interruption */
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writel_relaxed(0x1, hva->regs + HVA_HIF_REG_IT_ACK);
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return IRQ_WAKE_THREAD;
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}
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static irqreturn_t hva_hw_its_irq_thread(int irq, void *arg)
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{
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struct hva_dev *hva = arg;
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struct device *dev = hva_to_dev(hva);
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u32 status = hva->sts_reg & 0xFF;
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u8 ctx_id = 0;
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struct hva_ctx *ctx = NULL;
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dev_dbg(dev, "%s %s: status: 0x%02x fifo level: 0x%02x\n",
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HVA_PREFIX, __func__, hva->sts_reg & 0xFF, hva->sfl_reg & 0xF);
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/*
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* status: task_id[31:16] client_id[15:8] status[7:0]
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* the context identifier is retrieved from the client identifier
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*/
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ctx_id = (hva->sts_reg & 0xFF00) >> 8;
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if (ctx_id >= HVA_MAX_INSTANCES) {
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dev_err(dev, "%s %s: bad context identifier: %d\n",
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ctx->name, __func__, ctx_id);
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ctx->hw_err = true;
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goto out;
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}
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ctx = hva->instances[ctx_id];
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if (!ctx)
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goto out;
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switch (status) {
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case NO_ERROR:
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dev_dbg(dev, "%s %s: no error\n",
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ctx->name, __func__);
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ctx->hw_err = false;
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break;
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case H264_SLICE_READY:
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dev_dbg(dev, "%s %s: h264 slice ready\n",
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ctx->name, __func__);
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ctx->hw_err = false;
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break;
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case H264_FRAME_SKIPPED:
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dev_dbg(dev, "%s %s: h264 frame skipped\n",
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ctx->name, __func__);
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ctx->hw_err = false;
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break;
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case H264_BITSTREAM_OVERSIZE:
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dev_err(dev, "%s %s:h264 bitstream oversize\n",
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ctx->name, __func__);
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ctx->hw_err = true;
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break;
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case H264_SLICE_LIMIT_SIZE:
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dev_err(dev, "%s %s: h264 slice limit size is reached\n",
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ctx->name, __func__);
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ctx->hw_err = true;
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break;
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case H264_MAX_SLICE_NUMBER:
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dev_err(dev, "%s %s: h264 max slice number is reached\n",
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ctx->name, __func__);
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ctx->hw_err = true;
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break;
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case TASK_LIST_FULL:
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dev_err(dev, "%s %s:task list full\n",
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ctx->name, __func__);
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ctx->hw_err = true;
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break;
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case UNKNOWN_COMMAND:
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dev_err(dev, "%s %s: command not known\n",
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ctx->name, __func__);
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ctx->hw_err = true;
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break;
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case WRONG_CODEC_OR_RESOLUTION:
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dev_err(dev, "%s %s: wrong codec or resolution\n",
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ctx->name, __func__);
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ctx->hw_err = true;
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break;
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default:
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dev_err(dev, "%s %s: status not recognized\n",
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ctx->name, __func__);
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ctx->hw_err = true;
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break;
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}
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out:
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complete(&hva->interrupt);
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return IRQ_HANDLED;
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}
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static irqreturn_t hva_hw_err_interrupt(int irq, void *data)
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{
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struct hva_dev *hva = data;
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/* read status registers */
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hva->sts_reg = readl_relaxed(hva->regs + HVA_HIF_FIFO_STS);
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hva->sfl_reg = readl_relaxed(hva->regs + HVA_HIF_REG_SFL);
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/* read error registers */
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hva->lmi_err_reg = readl_relaxed(hva->regs + HVA_HIF_REG_LMI_ERR);
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hva->emi_err_reg = readl_relaxed(hva->regs + HVA_HIF_REG_EMI_ERR);
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hva->hec_mif_err_reg = readl_relaxed(hva->regs +
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HVA_HIF_REG_HEC_MIF_ERR);
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/* acknowledge interruption */
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writel_relaxed(0x1, hva->regs + HVA_HIF_REG_IT_ACK);
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return IRQ_WAKE_THREAD;
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}
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static irqreturn_t hva_hw_err_irq_thread(int irq, void *arg)
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{
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struct hva_dev *hva = arg;
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struct device *dev = hva_to_dev(hva);
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u8 ctx_id = 0;
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struct hva_ctx *ctx;
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dev_dbg(dev, "%s status: 0x%02x fifo level: 0x%02x\n",
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HVA_PREFIX, hva->sts_reg & 0xFF, hva->sfl_reg & 0xF);
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/*
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* status: task_id[31:16] client_id[15:8] status[7:0]
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* the context identifier is retrieved from the client identifier
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*/
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ctx_id = (hva->sts_reg & 0xFF00) >> 8;
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if (ctx_id >= HVA_MAX_INSTANCES) {
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dev_err(dev, "%s bad context identifier: %d\n", HVA_PREFIX,
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ctx_id);
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goto out;
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}
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ctx = hva->instances[ctx_id];
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if (!ctx)
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goto out;
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if (hva->lmi_err_reg) {
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dev_err(dev, "%s local memory interface error: 0x%08x\n",
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ctx->name, hva->lmi_err_reg);
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ctx->hw_err = true;
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}
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if (hva->emi_err_reg) {
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dev_err(dev, "%s external memory interface error: 0x%08x\n",
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ctx->name, hva->emi_err_reg);
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ctx->hw_err = true;
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}
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if (hva->hec_mif_err_reg) {
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dev_err(dev, "%s hec memory interface error: 0x%08x\n",
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ctx->name, hva->hec_mif_err_reg);
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ctx->hw_err = true;
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}
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out:
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complete(&hva->interrupt);
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return IRQ_HANDLED;
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}
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static unsigned long int hva_hw_get_ip_version(struct hva_dev *hva)
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{
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struct device *dev = hva_to_dev(hva);
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unsigned long int version;
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if (pm_runtime_get_sync(dev) < 0) {
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dev_err(dev, "%s failed to get pm_runtime\n", HVA_PREFIX);
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mutex_unlock(&hva->protect_mutex);
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return -EFAULT;
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}
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version = readl_relaxed(hva->regs + HVA_HIF_REG_VERSION) &
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VERSION_ID_MASK;
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pm_runtime_put_autosuspend(dev);
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switch (version) {
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case HVA_VERSION_V400:
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dev_dbg(dev, "%s IP hardware version 0x%lx\n",
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HVA_PREFIX, version);
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break;
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default:
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dev_err(dev, "%s unknown IP hardware version 0x%lx\n",
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HVA_PREFIX, version);
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version = HVA_VERSION_UNKNOWN;
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break;
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}
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return version;
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}
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int hva_hw_probe(struct platform_device *pdev, struct hva_dev *hva)
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{
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struct device *dev = &pdev->dev;
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struct resource *regs;
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struct resource *esram;
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int ret;
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WARN_ON(!hva);
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/* get memory for registers */
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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hva->regs = devm_ioremap_resource(dev, regs);
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if (IS_ERR(hva->regs)) {
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dev_err(dev, "%s failed to get regs\n", HVA_PREFIX);
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return PTR_ERR(hva->regs);
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}
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/* get memory for esram */
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esram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!esram) {
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dev_err(dev, "%s failed to get esram\n", HVA_PREFIX);
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return -ENODEV;
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}
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hva->esram_addr = esram->start;
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hva->esram_size = resource_size(esram);
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dev_info(dev, "%s esram reserved for address: 0x%x size:%d\n",
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HVA_PREFIX, hva->esram_addr, hva->esram_size);
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/* get clock resource */
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hva->clk = devm_clk_get(dev, "clk_hva");
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if (IS_ERR(hva->clk)) {
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dev_err(dev, "%s failed to get clock\n", HVA_PREFIX);
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return PTR_ERR(hva->clk);
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}
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ret = clk_prepare(hva->clk);
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if (ret < 0) {
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dev_err(dev, "%s failed to prepare clock\n", HVA_PREFIX);
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hva->clk = ERR_PTR(-EINVAL);
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return ret;
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}
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/* get status interruption resource */
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ret = platform_get_irq(pdev, 0);
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if (ret < 0) {
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dev_err(dev, "%s failed to get status IRQ\n", HVA_PREFIX);
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goto err_clk;
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}
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hva->irq_its = ret;
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ret = devm_request_threaded_irq(dev, hva->irq_its, hva_hw_its_interrupt,
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hva_hw_its_irq_thread,
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IRQF_ONESHOT,
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"hva_its_irq", hva);
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if (ret) {
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dev_err(dev, "%s failed to install status IRQ 0x%x\n",
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HVA_PREFIX, hva->irq_its);
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goto err_clk;
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}
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disable_irq(hva->irq_its);
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/* get error interruption resource */
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ret = platform_get_irq(pdev, 1);
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if (ret < 0) {
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dev_err(dev, "%s failed to get error IRQ\n", HVA_PREFIX);
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goto err_clk;
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}
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hva->irq_err = ret;
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ret = devm_request_threaded_irq(dev, hva->irq_err, hva_hw_err_interrupt,
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hva_hw_err_irq_thread,
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IRQF_ONESHOT,
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"hva_err_irq", hva);
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if (ret) {
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dev_err(dev, "%s failed to install error IRQ 0x%x\n",
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HVA_PREFIX, hva->irq_err);
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goto err_clk;
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}
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disable_irq(hva->irq_err);
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/* initialise protection mutex */
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mutex_init(&hva->protect_mutex);
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/* initialise completion signal */
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init_completion(&hva->interrupt);
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/* initialise runtime power management */
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pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_DELAY_MS);
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pm_runtime_use_autosuspend(dev);
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pm_runtime_set_suspended(dev);
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pm_runtime_enable(dev);
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ret = pm_runtime_get_sync(dev);
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if (ret < 0) {
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dev_err(dev, "%s failed to set PM\n", HVA_PREFIX);
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goto err_clk;
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}
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/* check IP hardware version */
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hva->ip_version = hva_hw_get_ip_version(hva);
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if (hva->ip_version == HVA_VERSION_UNKNOWN) {
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ret = -EINVAL;
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goto err_pm;
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}
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dev_info(dev, "%s found hva device (version 0x%lx)\n", HVA_PREFIX,
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hva->ip_version);
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return 0;
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err_pm:
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pm_runtime_put(dev);
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err_clk:
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if (hva->clk)
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clk_unprepare(hva->clk);
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return ret;
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}
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void hva_hw_remove(struct hva_dev *hva)
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{
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struct device *dev = hva_to_dev(hva);
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disable_irq(hva->irq_its);
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disable_irq(hva->irq_err);
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pm_runtime_put_autosuspend(dev);
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pm_runtime_disable(dev);
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}
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int hva_hw_runtime_suspend(struct device *dev)
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{
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struct hva_dev *hva = dev_get_drvdata(dev);
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clk_disable_unprepare(hva->clk);
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return 0;
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}
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int hva_hw_runtime_resume(struct device *dev)
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{
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struct hva_dev *hva = dev_get_drvdata(dev);
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if (clk_prepare_enable(hva->clk)) {
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dev_err(hva->dev, "%s failed to prepare hva clk\n",
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HVA_PREFIX);
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return -EINVAL;
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}
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if (clk_set_rate(hva->clk, CLK_RATE)) {
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dev_err(dev, "%s failed to set clock frequency\n",
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HVA_PREFIX);
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return -EINVAL;
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}
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return 0;
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}
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int hva_hw_execute_task(struct hva_ctx *ctx, enum hva_hw_cmd_type cmd,
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struct hva_buffer *task)
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{
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struct hva_dev *hva = ctx_to_hdev(ctx);
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struct device *dev = hva_to_dev(hva);
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u8 client_id = ctx->id;
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int ret;
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u32 reg = 0;
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mutex_lock(&hva->protect_mutex);
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/* enable irqs */
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enable_irq(hva->irq_its);
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enable_irq(hva->irq_err);
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if (pm_runtime_get_sync(dev) < 0) {
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dev_err(dev, "%s failed to get pm_runtime\n", ctx->name);
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ctx->sys_errors++;
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ret = -EFAULT;
|
|
goto out;
|
|
}
|
|
|
|
reg = readl_relaxed(hva->regs + HVA_HIF_REG_CLK_GATING);
|
|
switch (cmd) {
|
|
case H264_ENC:
|
|
reg |= CLK_GATING_HVC;
|
|
break;
|
|
default:
|
|
dev_dbg(dev, "%s unknown command 0x%x\n", ctx->name, cmd);
|
|
ctx->encode_errors++;
|
|
ret = -EFAULT;
|
|
goto out;
|
|
}
|
|
writel_relaxed(reg, hva->regs + HVA_HIF_REG_CLK_GATING);
|
|
|
|
dev_dbg(dev, "%s %s: write configuration registers\n", ctx->name,
|
|
__func__);
|
|
|
|
/* byte swap config */
|
|
writel_relaxed(BSM_CFG_VAL1, hva->regs + HVA_HIF_REG_BSM);
|
|
|
|
/* define Max Opcode Size and Max Message Size for LMI and EMI */
|
|
writel_relaxed(MIF_CFG_VAL3, hva->regs + HVA_HIF_REG_MIF_CFG);
|
|
writel_relaxed(HEC_MIF_CFG_VAL, hva->regs + HVA_HIF_REG_HEC_MIF_CFG);
|
|
|
|
/*
|
|
* command FIFO: task_id[31:16] client_id[15:8] command_type[7:0]
|
|
* the context identifier is provided as client identifier to the
|
|
* hardware, and is retrieved in the interrupt functions from the
|
|
* status register
|
|
*/
|
|
dev_dbg(dev, "%s %s: send task (cmd: %d, task_desc: %pad)\n",
|
|
ctx->name, __func__, cmd + (client_id << 8), &task->paddr);
|
|
writel_relaxed(cmd + (client_id << 8), hva->regs + HVA_HIF_FIFO_CMD);
|
|
writel_relaxed(task->paddr, hva->regs + HVA_HIF_FIFO_CMD);
|
|
|
|
if (!wait_for_completion_timeout(&hva->interrupt,
|
|
msecs_to_jiffies(2000))) {
|
|
dev_err(dev, "%s %s: time out on completion\n", ctx->name,
|
|
__func__);
|
|
ctx->encode_errors++;
|
|
ret = -EFAULT;
|
|
goto out;
|
|
}
|
|
|
|
/* get encoding status */
|
|
ret = ctx->hw_err ? -EFAULT : 0;
|
|
|
|
ctx->encode_errors += ctx->hw_err ? 1 : 0;
|
|
|
|
out:
|
|
disable_irq(hva->irq_its);
|
|
disable_irq(hva->irq_err);
|
|
|
|
switch (cmd) {
|
|
case H264_ENC:
|
|
reg &= ~CLK_GATING_HVC;
|
|
writel_relaxed(reg, hva->regs + HVA_HIF_REG_CLK_GATING);
|
|
break;
|
|
default:
|
|
dev_dbg(dev, "%s unknown command 0x%x\n", ctx->name, cmd);
|
|
}
|
|
|
|
pm_runtime_put_autosuspend(dev);
|
|
mutex_unlock(&hva->protect_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_VIDEO_STI_HVA_DEBUGFS
|
|
#define DUMP(reg) seq_printf(s, "%-30s: 0x%08X\n",\
|
|
#reg, readl_relaxed(hva->regs + reg))
|
|
|
|
void hva_hw_dump_regs(struct hva_dev *hva, struct seq_file *s)
|
|
{
|
|
struct device *dev = hva_to_dev(hva);
|
|
|
|
mutex_lock(&hva->protect_mutex);
|
|
|
|
if (pm_runtime_get_sync(dev) < 0) {
|
|
seq_puts(s, "Cannot wake up IP\n");
|
|
mutex_unlock(&hva->protect_mutex);
|
|
return;
|
|
}
|
|
|
|
seq_printf(s, "Registers:\nReg @ = 0x%p\n", hva->regs);
|
|
|
|
DUMP(HVA_HIF_REG_RST);
|
|
DUMP(HVA_HIF_REG_RST_ACK);
|
|
DUMP(HVA_HIF_REG_MIF_CFG);
|
|
DUMP(HVA_HIF_REG_HEC_MIF_CFG);
|
|
DUMP(HVA_HIF_REG_CFL);
|
|
DUMP(HVA_HIF_REG_SFL);
|
|
DUMP(HVA_HIF_REG_LMI_ERR);
|
|
DUMP(HVA_HIF_REG_EMI_ERR);
|
|
DUMP(HVA_HIF_REG_HEC_MIF_ERR);
|
|
DUMP(HVA_HIF_REG_HEC_STS);
|
|
DUMP(HVA_HIF_REG_HVC_STS);
|
|
DUMP(HVA_HIF_REG_HJE_STS);
|
|
DUMP(HVA_HIF_REG_CNT);
|
|
DUMP(HVA_HIF_REG_HEC_CHKSYN_DIS);
|
|
DUMP(HVA_HIF_REG_CLK_GATING);
|
|
DUMP(HVA_HIF_REG_VERSION);
|
|
|
|
pm_runtime_put_autosuspend(dev);
|
|
mutex_unlock(&hva->protect_mutex);
|
|
}
|
|
#endif
|
|
|