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348 lines
6.3 KiB
348 lines
6.3 KiB
config IRQCHIP
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def_bool y
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depends on OF_IRQ
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config ARM_GIC
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bool
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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select MULTI_IRQ_HANDLER
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config ARM_GIC_PM
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bool
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depends on PM
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select ARM_GIC
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select PM_CLK
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config ARM_GIC_MAX_NR
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int
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default 2 if ARCH_REALVIEW
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default 1
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config ARM_GIC_V2M
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bool
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depends on PCI
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select ARM_GIC
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select PCI_MSI
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config GIC_NON_BANKED
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bool
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config ARM_GIC_V3
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select IRQ_DOMAIN_HIERARCHY
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select PARTITION_PERCPU
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select QCOM_SHOW_RESUME_IRQ
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config ARM_GIC_V3_ITS
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bool
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depends on PCI
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depends on PCI_MSI
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config ARM_GIC_V3_ACL
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bool "GICv3 Access control"
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depends on ARM_GIC_V3
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help
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Access to GIC ITS address space is controlled by EL2.
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Kernel has no permission to access GIC ITS address space.
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If you wish to enforce the Acces control then set this
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option to Y, if you are unsure please say N.
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config ARM_NVIC
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bool
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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select GENERIC_IRQ_CHIP
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config ARM_VIC
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config ARM_VIC_NR
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int
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default 4 if ARCH_S5PV210
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default 2
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depends on ARM_VIC
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help
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The maximum number of VICs available in the system, for
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power management.
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config ARMADA_370_XP_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select PCI_MSI if PCI
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config ALPINE_MSI
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bool
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depends on PCI
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select PCI_MSI
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select GENERIC_IRQ_CHIP
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config ATMEL_AIC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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config ATMEL_AIC5_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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config I8259
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bool
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select IRQ_DOMAIN
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config BCM6345_L1_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config BCM7038_L1_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config BCM7120_L2_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config BRCMSTB_L2_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config QCOM_SHOW_RESUME_IRQ
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bool "Enable logging of interrupts that could have caused resume"
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depends on ARM_GIC
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default n
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help
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This option logs wake up interrupts that have triggered just before
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the resume loop unrolls. It helps to debug to know any unnecessary
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wake up interrupts that causes system to come out of low power modes.
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Say Y if you want to debug why the system resumed.
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config DW_APB_ICTL
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config FARADAY_FTINTC010
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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config HISILICON_IRQ_MBIGEN
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bool
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select ARM_GIC_V3
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select ARM_GIC_V3_ITS
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config IMGPDC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config IRQ_MIPS_CPU
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bool
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select GENERIC_IRQ_CHIP
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select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config CLPS711X_IRQCHIP
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bool
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depends on ARCH_CLPS711X
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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default y
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config OR1K_PIC
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bool
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select IRQ_DOMAIN
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config OMAP_IRQCHIP
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config ORION_IRQCHIP
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config PIC32_EVIC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config JCORE_AIC
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bool "J-Core integrated AIC" if COMPILE_TEST
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depends on OF
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select IRQ_DOMAIN
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help
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Support for the J-Core integrated AIC.
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config RENESAS_INTC_IRQPIN
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bool
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select IRQ_DOMAIN
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config RENESAS_IRQC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config ST_IRQCHIP
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bool
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select REGMAP
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select MFD_SYSCON
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help
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Enables SysCfg Controlled IRQs on STi based platforms.
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config TANGO_IRQ
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config TACNA_IRQ
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tristate
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config TB10X_IRQC
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config TS4800_IRQ
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tristate "TS-4800 IRQ controller"
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select IRQ_DOMAIN
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depends on HAS_IOMEM
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depends on SOC_IMX51 || COMPILE_TEST
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help
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Support for the TS-4800 FPGA IRQ controller
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config VERSATILE_FPGA_IRQ
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bool
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select IRQ_DOMAIN
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config VERSATILE_FPGA_IRQ_NR
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int
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default 4
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depends on VERSATILE_FPGA_IRQ
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config XTENSA_MX
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config XILINX_INTC
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bool
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select IRQ_DOMAIN
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config IRQ_CROSSBAR
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bool
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help
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Support for a CROSSBAR ip that precedes the main interrupt controller.
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The primary irqchip invokes the crossbar's callback which inturn allocates
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a free irq and configures the IP. Thus the peripheral interrupts are
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routed to one of the free irqchip interrupt lines.
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config KEYSTONE_IRQ
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tristate "Keystone 2 IRQ controller IP"
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depends on ARCH_KEYSTONE
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help
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Support for Texas Instruments Keystone 2 IRQ controller IP which
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is part of the Keystone 2 IPC mechanism
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config MIPS_GIC
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bool
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select GENERIC_IRQ_IPI
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select IRQ_DOMAIN_HIERARCHY
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select MIPS_CM
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config INGENIC_IRQ
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bool
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depends on MACH_INGENIC
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default y
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config RENESAS_H8300H_INTC
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bool
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select IRQ_DOMAIN
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config RENESAS_H8S_INTC
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bool
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select IRQ_DOMAIN
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config IMX_GPCV2
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bool
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select IRQ_DOMAIN
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help
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Enables the wakeup IRQs for IMX platforms with GPCv2 block
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config IRQ_MXS
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def_bool y if MACH_ASM9260 || ARCH_MXS
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select IRQ_DOMAIN
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select STMP_DEVICE
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config MVEBU_GICP
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bool
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config MVEBU_ICU
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bool
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config MVEBU_ODMI
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bool
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select GENERIC_MSI_IRQ_DOMAIN
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config MVEBU_PIC
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bool
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config LS_SCFG_MSI
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def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
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depends on PCI && PCI_MSI
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config PARTITION_PERCPU
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bool
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config EZNPS_GIC
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bool "NPS400 Global Interrupt Manager (GIM)"
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depends on ARC || (COMPILE_TEST && !64BIT)
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select IRQ_DOMAIN
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help
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Support the EZchip NPS400 global interrupt controller
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config STM32_EXTI
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bool
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select IRQ_DOMAIN
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config QCOM_IRQ_COMBINER
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bool "QCOM IRQ combiner support"
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depends on ARCH_QCOM && ACPI
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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help
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Say yes here to add support for the IRQ combiner devices embedded
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in Qualcomm Technologies chips.
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config IRQ_UNIPHIER_AIDET
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bool "UniPhier AIDET support" if COMPILE_TEST
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depends on ARCH_UNIPHIER || COMPILE_TEST
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default ARCH_UNIPHIER
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select IRQ_DOMAIN_HIERARCHY
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help
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Support for the UniPhier AIDET (ARM Interrupt Detector).
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source "drivers/irqchip/qcom/Kconfig"
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