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765 lines
26 KiB
765 lines
26 KiB
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _INTEL_RINGBUFFER_H_
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#define _INTEL_RINGBUFFER_H_
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#include <linux/hashtable.h>
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#include "i915_gem_batch_pool.h"
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#include "i915_gem_request.h"
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#include "i915_gem_timeline.h"
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#include "i915_selftest.h"
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#define I915_CMD_HASH_ORDER 9
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/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
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* but keeps the logic simple. Indeed, the whole purpose of this macro is just
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* to give some inclination as to some of the magic values used in the various
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* workarounds!
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*/
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#define CACHELINE_BYTES 64
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#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
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struct intel_hw_status_page {
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struct i915_vma *vma;
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u32 *page_addr;
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u32 ggtt_offset;
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};
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#define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
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#define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
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#define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
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#define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
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#define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
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#define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
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#define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
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#define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
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#define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
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#define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
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#define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
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#define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
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/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
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* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
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*/
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#define gen8_semaphore_seqno_size sizeof(uint64_t)
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#define GEN8_SEMAPHORE_OFFSET(__from, __to) \
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(((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size)
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#define GEN8_SIGNAL_OFFSET(__ring, to) \
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(dev_priv->semaphore->node.start + \
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GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
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#define GEN8_WAIT_OFFSET(__ring, from) \
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(dev_priv->semaphore->node.start + \
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GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
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enum intel_engine_hangcheck_action {
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ENGINE_IDLE = 0,
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ENGINE_WAIT,
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ENGINE_ACTIVE_SEQNO,
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ENGINE_ACTIVE_HEAD,
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ENGINE_ACTIVE_SUBUNITS,
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ENGINE_WAIT_KICK,
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ENGINE_DEAD,
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};
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static inline const char *
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hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
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{
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switch (a) {
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case ENGINE_IDLE:
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return "idle";
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case ENGINE_WAIT:
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return "wait";
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case ENGINE_ACTIVE_SEQNO:
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return "active seqno";
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case ENGINE_ACTIVE_HEAD:
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return "active head";
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case ENGINE_ACTIVE_SUBUNITS:
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return "active subunits";
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case ENGINE_WAIT_KICK:
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return "wait kick";
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case ENGINE_DEAD:
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return "dead";
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}
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return "unknown";
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}
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#define I915_MAX_SLICES 3
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#define I915_MAX_SUBSLICES 3
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#define instdone_slice_mask(dev_priv__) \
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(INTEL_GEN(dev_priv__) == 7 ? \
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1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
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#define instdone_subslice_mask(dev_priv__) \
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(INTEL_GEN(dev_priv__) == 7 ? \
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1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask)
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#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
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for ((slice__) = 0, (subslice__) = 0; \
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(slice__) < I915_MAX_SLICES; \
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(subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
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(slice__) += ((subslice__) == 0)) \
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for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
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(BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
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struct intel_instdone {
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u32 instdone;
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/* The following exist only in the RCS engine */
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u32 slice_common;
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u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES];
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u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES];
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};
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struct intel_engine_hangcheck {
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u64 acthd;
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u32 seqno;
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enum intel_engine_hangcheck_action action;
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unsigned long action_timestamp;
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int deadlock;
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struct intel_instdone instdone;
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struct drm_i915_gem_request *active_request;
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bool stalled;
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};
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struct intel_ring {
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struct i915_vma *vma;
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void *vaddr;
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struct list_head request_list;
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u32 head;
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u32 tail;
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u32 emit;
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u32 space;
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u32 size;
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u32 effective_size;
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};
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struct i915_gem_context;
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struct drm_i915_reg_table;
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/*
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* we use a single page to load ctx workarounds so all of these
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* values are referred in terms of dwords
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*
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* struct i915_wa_ctx_bb:
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* offset: specifies batch starting position, also helpful in case
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* if we want to have multiple batches at different offsets based on
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* some criteria. It is not a requirement at the moment but provides
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* an option for future use.
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* size: size of the batch in DWORDS
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*/
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struct i915_ctx_workarounds {
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struct i915_wa_ctx_bb {
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u32 offset;
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u32 size;
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} indirect_ctx, per_ctx;
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struct i915_vma *vma;
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};
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struct drm_i915_gem_request;
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struct intel_render_state;
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/*
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* Engine IDs definitions.
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* Keep instances of the same type engine together.
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*/
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enum intel_engine_id {
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RCS = 0,
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BCS,
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VCS,
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VCS2,
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#define _VCS(n) (VCS + (n))
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VECS
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};
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struct i915_priolist {
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struct rb_node node;
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struct list_head requests;
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int priority;
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};
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#define INTEL_ENGINE_CS_MAX_NAME 8
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struct intel_engine_cs {
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struct drm_i915_private *i915;
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char name[INTEL_ENGINE_CS_MAX_NAME];
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enum intel_engine_id id;
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unsigned int uabi_id;
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unsigned int hw_id;
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unsigned int guc_id;
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u8 class;
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u8 instance;
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u32 context_size;
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u32 mmio_base;
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unsigned int irq_shift;
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struct intel_ring *buffer;
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struct intel_timeline *timeline;
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struct intel_render_state *render_state;
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atomic_t irq_count;
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unsigned long irq_posted;
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#define ENGINE_IRQ_BREADCRUMB 0
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#define ENGINE_IRQ_EXECLIST 1
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/* Rather than have every client wait upon all user interrupts,
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* with the herd waking after every interrupt and each doing the
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* heavyweight seqno dance, we delegate the task (of being the
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* bottom-half of the user interrupt) to the first client. After
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* every interrupt, we wake up one client, who does the heavyweight
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* coherent seqno read and either goes back to sleep (if incomplete),
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* or wakes up all the completed clients in parallel, before then
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* transferring the bottom-half status to the next client in the queue.
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*
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* Compared to walking the entire list of waiters in a single dedicated
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* bottom-half, we reduce the latency of the first waiter by avoiding
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* a context switch, but incur additional coherent seqno reads when
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* following the chain of request breadcrumbs. Since it is most likely
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* that we have a single client waiting on each seqno, then reducing
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* the overhead of waking that client is much preferred.
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*/
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struct intel_breadcrumbs {
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spinlock_t irq_lock; /* protects irq_*; irqsafe */
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struct intel_wait *irq_wait; /* oldest waiter by retirement */
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spinlock_t rb_lock; /* protects the rb and wraps irq_lock */
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struct rb_root waiters; /* sorted by retirement, priority */
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struct rb_root signals; /* sorted by retirement */
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struct task_struct *signaler; /* used for fence signalling */
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struct drm_i915_gem_request __rcu *first_signal;
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struct timer_list fake_irq; /* used after a missed interrupt */
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struct timer_list hangcheck; /* detect missed interrupts */
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unsigned int hangcheck_interrupts;
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bool irq_armed : 1;
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bool irq_enabled : 1;
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I915_SELFTEST_DECLARE(bool mock : 1);
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} breadcrumbs;
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/*
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* A pool of objects to use as shadow copies of client batch buffers
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* when the command parser is enabled. Prevents the client from
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* modifying the batch contents after software parsing.
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*/
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struct i915_gem_batch_pool batch_pool;
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struct intel_hw_status_page status_page;
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struct i915_ctx_workarounds wa_ctx;
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struct i915_vma *scratch;
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u32 irq_keep_mask; /* always keep these interrupts */
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u32 irq_enable_mask; /* bitmask to enable ring interrupt */
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void (*irq_enable)(struct intel_engine_cs *engine);
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void (*irq_disable)(struct intel_engine_cs *engine);
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int (*init_hw)(struct intel_engine_cs *engine);
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void (*reset_hw)(struct intel_engine_cs *engine,
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struct drm_i915_gem_request *req);
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void (*set_default_submission)(struct intel_engine_cs *engine);
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struct intel_ring *(*context_pin)(struct intel_engine_cs *engine,
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struct i915_gem_context *ctx);
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void (*context_unpin)(struct intel_engine_cs *engine,
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struct i915_gem_context *ctx);
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int (*request_alloc)(struct drm_i915_gem_request *req);
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int (*init_context)(struct drm_i915_gem_request *req);
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int (*emit_flush)(struct drm_i915_gem_request *request,
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u32 mode);
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#define EMIT_INVALIDATE BIT(0)
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#define EMIT_FLUSH BIT(1)
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#define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
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int (*emit_bb_start)(struct drm_i915_gem_request *req,
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u64 offset, u32 length,
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unsigned int dispatch_flags);
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#define I915_DISPATCH_SECURE BIT(0)
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#define I915_DISPATCH_PINNED BIT(1)
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#define I915_DISPATCH_RS BIT(2)
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void (*emit_breadcrumb)(struct drm_i915_gem_request *req,
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u32 *cs);
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int emit_breadcrumb_sz;
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/* Pass the request to the hardware queue (e.g. directly into
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* the legacy ringbuffer or to the end of an execlist).
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*
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* This is called from an atomic context with irqs disabled; must
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* be irq safe.
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*/
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void (*submit_request)(struct drm_i915_gem_request *req);
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/* Call when the priority on a request has changed and it and its
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* dependencies may need rescheduling. Note the request itself may
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* not be ready to run!
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*
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* Called under the struct_mutex.
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*/
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void (*schedule)(struct drm_i915_gem_request *request,
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int priority);
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/* Some chipsets are not quite as coherent as advertised and need
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* an expensive kick to force a true read of the up-to-date seqno.
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* However, the up-to-date seqno is not always required and the last
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* seen value is good enough. Note that the seqno will always be
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* monotonic, even if not coherent.
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*/
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void (*irq_seqno_barrier)(struct intel_engine_cs *engine);
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void (*cleanup)(struct intel_engine_cs *engine);
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/* GEN8 signal/wait table - never trust comments!
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* signal to signal to signal to signal to signal to
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* RCS VCS BCS VECS VCS2
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* --------------------------------------------------------------------
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* RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
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* |-------------------------------------------------------------------
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* VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
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* |-------------------------------------------------------------------
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* BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
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* |-------------------------------------------------------------------
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* VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
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* |-------------------------------------------------------------------
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* VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
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* |-------------------------------------------------------------------
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*
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* Generalization:
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* f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
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* ie. transpose of g(x, y)
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*
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* sync from sync from sync from sync from sync from
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* RCS VCS BCS VECS VCS2
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* --------------------------------------------------------------------
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* RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
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* |-------------------------------------------------------------------
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* VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
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* |-------------------------------------------------------------------
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* BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
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* |-------------------------------------------------------------------
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* VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
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* |-------------------------------------------------------------------
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* VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
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* |-------------------------------------------------------------------
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*
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* Generalization:
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* g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
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* ie. transpose of f(x, y)
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*/
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struct {
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union {
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#define GEN6_SEMAPHORE_LAST VECS_HW
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#define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1)
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#define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0)
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struct {
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/* our mbox written by others */
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u32 wait[GEN6_NUM_SEMAPHORES];
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/* mboxes this ring signals to */
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i915_reg_t signal[GEN6_NUM_SEMAPHORES];
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} mbox;
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u64 signal_ggtt[I915_NUM_ENGINES];
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};
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/* AKA wait() */
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int (*sync_to)(struct drm_i915_gem_request *req,
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struct drm_i915_gem_request *signal);
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u32 *(*signal)(struct drm_i915_gem_request *req, u32 *cs);
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} semaphore;
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/* Execlists */
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struct tasklet_struct irq_tasklet;
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struct i915_priolist default_priolist;
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bool no_priolist;
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struct execlist_port {
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struct drm_i915_gem_request *request_count;
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#define EXECLIST_COUNT_BITS 2
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#define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
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#define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
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#define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
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#define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
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#define port_set(p, packed) ((p)->request_count = (packed))
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#define port_isset(p) ((p)->request_count)
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#define port_index(p, e) ((p) - (e)->execlist_port)
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GEM_DEBUG_DECL(u32 context_id);
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} execlist_port[2];
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struct rb_root execlist_queue;
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struct rb_node *execlist_first;
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unsigned int fw_domains;
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/* Contexts are pinned whilst they are active on the GPU. The last
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* context executed remains active whilst the GPU is idle - the
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* switch away and write to the context object only occurs on the
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* next execution. Contexts are only unpinned on retirement of the
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* following request ensuring that we can always write to the object
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* on the context switch even after idling. Across suspend, we switch
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* to the kernel context and trash it as the save may not happen
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* before the hardware is powered down.
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*/
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struct i915_gem_context *last_retired_context;
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/* We track the current MI_SET_CONTEXT in order to eliminate
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* redudant context switches. This presumes that requests are not
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* reordered! Or when they are the tracking is updated along with
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* the emission of individual requests into the legacy command
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* stream (ring).
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*/
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struct i915_gem_context *legacy_active_context;
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/* status_notifier: list of callbacks for context-switch changes */
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struct atomic_notifier_head context_status_notifier;
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struct intel_engine_hangcheck hangcheck;
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#define I915_ENGINE_USING_CMD_PARSER BIT(0)
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#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(3)
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unsigned int flags;
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/*
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* Table of commands the command parser needs to know about
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* for this engine.
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*/
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DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
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/*
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* Table of registers allowed in commands that read/write registers.
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*/
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const struct drm_i915_reg_table *reg_tables;
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int reg_table_count;
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/*
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* Returns the bitmask for the length field of the specified command.
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* Return 0 for an unrecognized/invalid command.
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*
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* If the command parser finds an entry for a command in the engine's
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* cmd_tables, it gets the command's length based on the table entry.
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* If not, it calls this function to determine the per-engine length
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* field encoding for the command (i.e. different opcode ranges use
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* certain bits to encode the command length in the header).
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*/
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u32 (*get_cmd_length_mask)(u32 cmd_header);
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};
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static inline bool
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|
intel_engine_using_cmd_parser(const struct intel_engine_cs *engine)
|
|
{
|
|
return engine->flags & I915_ENGINE_USING_CMD_PARSER;
|
|
}
|
|
|
|
static inline bool
|
|
intel_engine_requires_cmd_parser(const struct intel_engine_cs *engine)
|
|
{
|
|
return engine->flags & I915_ENGINE_REQUIRES_CMD_PARSER;
|
|
}
|
|
|
|
static inline unsigned int
|
|
intel_engine_flag(const struct intel_engine_cs *engine)
|
|
{
|
|
return BIT(engine->id);
|
|
}
|
|
|
|
static inline u32
|
|
intel_read_status_page(struct intel_engine_cs *engine, int reg)
|
|
{
|
|
/* Ensure that the compiler doesn't optimize away the load. */
|
|
return READ_ONCE(engine->status_page.page_addr[reg]);
|
|
}
|
|
|
|
static inline void
|
|
intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
|
|
{
|
|
/* Writing into the status page should be done sparingly. Since
|
|
* we do when we are uncertain of the device state, we take a bit
|
|
* of extra paranoia to try and ensure that the HWS takes the value
|
|
* we give and that it doesn't end up trapped inside the CPU!
|
|
*/
|
|
if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
|
|
mb();
|
|
clflush(&engine->status_page.page_addr[reg]);
|
|
engine->status_page.page_addr[reg] = value;
|
|
clflush(&engine->status_page.page_addr[reg]);
|
|
mb();
|
|
} else {
|
|
WRITE_ONCE(engine->status_page.page_addr[reg], value);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Reads a dword out of the status page, which is written to from the command
|
|
* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
|
|
* MI_STORE_DATA_IMM.
|
|
*
|
|
* The following dwords have a reserved meaning:
|
|
* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
|
|
* 0x04: ring 0 head pointer
|
|
* 0x05: ring 1 head pointer (915-class)
|
|
* 0x06: ring 2 head pointer (915-class)
|
|
* 0x10-0x1b: Context status DWords (GM45)
|
|
* 0x1f: Last written status offset. (GM45)
|
|
* 0x20-0x2f: Reserved (Gen6+)
|
|
*
|
|
* The area from dword 0x30 to 0x3ff is available for driver usage.
|
|
*/
|
|
#define I915_GEM_HWS_INDEX 0x30
|
|
#define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
|
|
#define I915_GEM_HWS_SCRATCH_INDEX 0x40
|
|
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
|
|
|
|
struct intel_ring *
|
|
intel_engine_create_ring(struct intel_engine_cs *engine, int size);
|
|
int intel_ring_pin(struct intel_ring *ring,
|
|
struct drm_i915_private *i915,
|
|
unsigned int offset_bias);
|
|
void intel_ring_reset(struct intel_ring *ring, u32 tail);
|
|
unsigned int intel_ring_update_space(struct intel_ring *ring);
|
|
void intel_ring_unpin(struct intel_ring *ring);
|
|
void intel_ring_free(struct intel_ring *ring);
|
|
|
|
void intel_engine_stop(struct intel_engine_cs *engine);
|
|
void intel_engine_cleanup(struct intel_engine_cs *engine);
|
|
|
|
void intel_legacy_submission_resume(struct drm_i915_private *dev_priv);
|
|
|
|
int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
|
|
|
|
u32 __must_check *intel_ring_begin(struct drm_i915_gem_request *req,
|
|
unsigned int n);
|
|
|
|
static inline void
|
|
intel_ring_advance(struct drm_i915_gem_request *req, u32 *cs)
|
|
{
|
|
/* Dummy function.
|
|
*
|
|
* This serves as a placeholder in the code so that the reader
|
|
* can compare against the preceding intel_ring_begin() and
|
|
* check that the number of dwords emitted matches the space
|
|
* reserved for the command packet (i.e. the value passed to
|
|
* intel_ring_begin()).
|
|
*/
|
|
GEM_BUG_ON((req->ring->vaddr + req->ring->emit) != cs);
|
|
}
|
|
|
|
static inline u32
|
|
intel_ring_wrap(const struct intel_ring *ring, u32 pos)
|
|
{
|
|
return pos & (ring->size - 1);
|
|
}
|
|
|
|
static inline u32
|
|
intel_ring_offset(const struct drm_i915_gem_request *req, void *addr)
|
|
{
|
|
/* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
|
|
u32 offset = addr - req->ring->vaddr;
|
|
GEM_BUG_ON(offset > req->ring->size);
|
|
return intel_ring_wrap(req->ring, offset);
|
|
}
|
|
|
|
static inline void
|
|
assert_ring_tail_valid(const struct intel_ring *ring, unsigned int tail)
|
|
{
|
|
/* We could combine these into a single tail operation, but keeping
|
|
* them as seperate tests will help identify the cause should one
|
|
* ever fire.
|
|
*/
|
|
GEM_BUG_ON(!IS_ALIGNED(tail, 8));
|
|
GEM_BUG_ON(tail >= ring->size);
|
|
|
|
/*
|
|
* "Ring Buffer Use"
|
|
* Gen2 BSpec "1. Programming Environment" / 1.4.4.6
|
|
* Gen3 BSpec "1c Memory Interface Functions" / 2.3.4.5
|
|
* Gen4+ BSpec "1c Memory Interface and Command Stream" / 5.3.4.5
|
|
* "If the Ring Buffer Head Pointer and the Tail Pointer are on the
|
|
* same cacheline, the Head Pointer must not be greater than the Tail
|
|
* Pointer."
|
|
*
|
|
* We use ring->head as the last known location of the actual RING_HEAD,
|
|
* it may have advanced but in the worst case it is equally the same
|
|
* as ring->head and so we should never program RING_TAIL to advance
|
|
* into the same cacheline as ring->head.
|
|
*/
|
|
#define cacheline(a) round_down(a, CACHELINE_BYTES)
|
|
GEM_BUG_ON(cacheline(tail) == cacheline(ring->head) &&
|
|
tail < ring->head);
|
|
#undef cacheline
|
|
}
|
|
|
|
static inline unsigned int
|
|
intel_ring_set_tail(struct intel_ring *ring, unsigned int tail)
|
|
{
|
|
/* Whilst writes to the tail are strictly order, there is no
|
|
* serialisation between readers and the writers. The tail may be
|
|
* read by i915_gem_request_retire() just as it is being updated
|
|
* by execlists, as although the breadcrumb is complete, the context
|
|
* switch hasn't been seen.
|
|
*/
|
|
assert_ring_tail_valid(ring, tail);
|
|
ring->tail = tail;
|
|
return tail;
|
|
}
|
|
|
|
void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno);
|
|
|
|
void intel_engine_setup_common(struct intel_engine_cs *engine);
|
|
int intel_engine_init_common(struct intel_engine_cs *engine);
|
|
int intel_engine_create_scratch(struct intel_engine_cs *engine, int size);
|
|
void intel_engine_cleanup_common(struct intel_engine_cs *engine);
|
|
|
|
int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
|
|
int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
|
|
int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
|
|
int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
|
|
|
|
u64 intel_engine_get_active_head(struct intel_engine_cs *engine);
|
|
u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine);
|
|
|
|
static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
|
|
{
|
|
return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
|
|
}
|
|
|
|
static inline u32 intel_engine_last_submit(struct intel_engine_cs *engine)
|
|
{
|
|
/* We are only peeking at the tail of the submit queue (and not the
|
|
* queue itself) in order to gain a hint as to the current active
|
|
* state of the engine. Callers are not expected to be taking
|
|
* engine->timeline->lock, nor are they expected to be concerned
|
|
* wtih serialising this hint with anything, so document it as
|
|
* a hint and nothing more.
|
|
*/
|
|
return READ_ONCE(engine->timeline->seqno);
|
|
}
|
|
|
|
int init_workarounds_ring(struct intel_engine_cs *engine);
|
|
int intel_ring_workarounds_emit(struct drm_i915_gem_request *req);
|
|
|
|
void intel_engine_get_instdone(struct intel_engine_cs *engine,
|
|
struct intel_instdone *instdone);
|
|
|
|
/*
|
|
* Arbitrary size for largest possible 'add request' sequence. The code paths
|
|
* are complex and variable. Empirical measurement shows that the worst case
|
|
* is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
|
|
* we need to allocate double the largest single packet within that emission
|
|
* to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
|
|
*/
|
|
#define MIN_SPACE_FOR_ADD_REQUEST 336
|
|
|
|
static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)
|
|
{
|
|
return engine->status_page.ggtt_offset + I915_GEM_HWS_INDEX_ADDR;
|
|
}
|
|
|
|
/* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
|
|
int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
|
|
|
|
static inline void intel_wait_init(struct intel_wait *wait,
|
|
struct drm_i915_gem_request *rq)
|
|
{
|
|
wait->tsk = current;
|
|
wait->request = rq;
|
|
}
|
|
|
|
static inline void intel_wait_init_for_seqno(struct intel_wait *wait, u32 seqno)
|
|
{
|
|
wait->tsk = current;
|
|
wait->seqno = seqno;
|
|
}
|
|
|
|
static inline bool intel_wait_has_seqno(const struct intel_wait *wait)
|
|
{
|
|
return wait->seqno;
|
|
}
|
|
|
|
static inline bool
|
|
intel_wait_update_seqno(struct intel_wait *wait, u32 seqno)
|
|
{
|
|
wait->seqno = seqno;
|
|
return intel_wait_has_seqno(wait);
|
|
}
|
|
|
|
static inline bool
|
|
intel_wait_update_request(struct intel_wait *wait,
|
|
const struct drm_i915_gem_request *rq)
|
|
{
|
|
return intel_wait_update_seqno(wait, i915_gem_request_global_seqno(rq));
|
|
}
|
|
|
|
static inline bool
|
|
intel_wait_check_seqno(const struct intel_wait *wait, u32 seqno)
|
|
{
|
|
return wait->seqno == seqno;
|
|
}
|
|
|
|
static inline bool
|
|
intel_wait_check_request(const struct intel_wait *wait,
|
|
const struct drm_i915_gem_request *rq)
|
|
{
|
|
return intel_wait_check_seqno(wait, i915_gem_request_global_seqno(rq));
|
|
}
|
|
|
|
static inline bool intel_wait_complete(const struct intel_wait *wait)
|
|
{
|
|
return RB_EMPTY_NODE(&wait->node);
|
|
}
|
|
|
|
bool intel_engine_add_wait(struct intel_engine_cs *engine,
|
|
struct intel_wait *wait);
|
|
void intel_engine_remove_wait(struct intel_engine_cs *engine,
|
|
struct intel_wait *wait);
|
|
void intel_engine_enable_signaling(struct drm_i915_gem_request *request,
|
|
bool wakeup);
|
|
void intel_engine_cancel_signaling(struct drm_i915_gem_request *request);
|
|
|
|
static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine)
|
|
{
|
|
return READ_ONCE(engine->breadcrumbs.irq_wait);
|
|
}
|
|
|
|
unsigned int intel_engine_wakeup(struct intel_engine_cs *engine);
|
|
#define ENGINE_WAKEUP_WAITER BIT(0)
|
|
#define ENGINE_WAKEUP_ASLEEP BIT(1)
|
|
|
|
void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
|
|
void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
|
|
|
|
void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
|
|
void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
|
|
bool intel_breadcrumbs_busy(struct intel_engine_cs *engine);
|
|
|
|
static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
|
|
{
|
|
memset(batch, 0, 6 * sizeof(u32));
|
|
|
|
batch[0] = GFX_OP_PIPE_CONTROL(6);
|
|
batch[1] = flags;
|
|
batch[2] = offset;
|
|
|
|
return batch + 6;
|
|
}
|
|
|
|
bool intel_engine_is_idle(struct intel_engine_cs *engine);
|
|
bool intel_engines_are_idle(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_engines_mark_idle(struct drm_i915_private *i915);
|
|
void intel_engines_reset_default_submission(struct drm_i915_private *i915);
|
|
|
|
static inline bool
|
|
__intel_engine_can_store_dword(unsigned int gen, unsigned int class)
|
|
{
|
|
if (gen <= 2)
|
|
return false; /* uses physical not virtual addresses */
|
|
|
|
if (gen == 6 && class == VIDEO_DECODE_CLASS)
|
|
return false; /* b0rked */
|
|
|
|
return true;
|
|
}
|
|
|
|
#endif /* _INTEL_RINGBUFFER_H_ */
|
|
|