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251 lines
7.4 KiB
251 lines
7.4 KiB
/*
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* ARC PGU DRM driver.
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*
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* Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <linux/clk.h>
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#include <linux/platform_data/simplefb.h>
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#include "arcpgu.h"
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#include "arcpgu_regs.h"
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#define ENCODE_PGU_XY(x, y) ((((x) - 1) << 16) | ((y) - 1))
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static struct simplefb_format supported_formats[] = {
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{ "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0}, DRM_FORMAT_RGB565 },
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{ "r8g8b8", 24, {16, 8}, {8, 8}, {0, 8}, {0, 0}, DRM_FORMAT_RGB888 },
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};
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static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
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{
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struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
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const struct drm_framebuffer *fb = crtc->primary->state->fb;
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uint32_t pixel_format = fb->format->format;
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struct simplefb_format *format = NULL;
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int i;
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for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
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if (supported_formats[i].fourcc == pixel_format)
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format = &supported_formats[i];
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}
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if (WARN_ON(!format))
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return;
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if (format->fourcc == DRM_FORMAT_RGB888)
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arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
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arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
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ARCPGU_MODE_RGB888_MASK);
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}
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static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
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.destroy = drm_crtc_cleanup,
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.set_config = drm_atomic_helper_set_config,
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.page_flip = drm_atomic_helper_page_flip,
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.reset = drm_atomic_helper_crtc_reset,
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.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
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};
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static enum drm_mode_status arc_pgu_crtc_mode_valid(struct drm_crtc *crtc,
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const struct drm_display_mode *mode)
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{
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struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
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long rate, clk_rate = mode->clock * 1000;
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long diff = clk_rate / 200; /* +-0.5% allowed by HDMI spec */
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rate = clk_round_rate(arcpgu->clk, clk_rate);
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if ((max(rate, clk_rate) - min(rate, clk_rate) < diff) && (rate > 0))
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return MODE_OK;
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return MODE_NOCLOCK;
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}
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static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
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{
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struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
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struct drm_display_mode *m = &crtc->state->adjusted_mode;
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u32 val;
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arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
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ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
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arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
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ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
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m->crtc_hsync_end - m->crtc_hdisplay));
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arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
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ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
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m->crtc_vsync_end - m->crtc_vdisplay));
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arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
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ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
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m->crtc_vblank_end - m->crtc_vblank_start));
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val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
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if (m->flags & DRM_MODE_FLAG_PVSYNC)
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val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
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else
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val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
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if (m->flags & DRM_MODE_FLAG_PHSYNC)
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val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
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else
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val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
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arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
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arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
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arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
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arc_pgu_set_pxl_fmt(crtc);
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clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
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}
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static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
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clk_prepare_enable(arcpgu->clk);
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arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
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arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
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ARCPGU_CTRL_ENABLE_MASK);
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}
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static void arc_pgu_crtc_atomic_disable(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
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if (!crtc->primary->fb)
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return;
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clk_disable_unprepare(arcpgu->clk);
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arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
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arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
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~ARCPGU_CTRL_ENABLE_MASK);
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}
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static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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struct drm_pending_vblank_event *event = crtc->state->event;
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if (event) {
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crtc->state->event = NULL;
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spin_lock_irq(&crtc->dev->event_lock);
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drm_crtc_send_vblank_event(crtc, event);
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spin_unlock_irq(&crtc->dev->event_lock);
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}
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}
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static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
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.mode_valid = arc_pgu_crtc_mode_valid,
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.mode_set = drm_helper_crtc_mode_set,
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.mode_set_base = drm_helper_crtc_mode_set_base,
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.mode_set_nofb = arc_pgu_crtc_mode_set_nofb,
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.atomic_begin = arc_pgu_crtc_atomic_begin,
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.atomic_enable = arc_pgu_crtc_atomic_enable,
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.atomic_disable = arc_pgu_crtc_atomic_disable,
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};
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static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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struct arcpgu_drm_private *arcpgu;
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struct drm_gem_cma_object *gem;
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if (!plane->state->crtc || !plane->state->fb)
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return;
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arcpgu = crtc_to_arcpgu_priv(plane->state->crtc);
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gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
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arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
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}
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static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
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.atomic_update = arc_pgu_plane_atomic_update,
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};
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static void arc_pgu_plane_destroy(struct drm_plane *plane)
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{
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drm_plane_helper_disable(plane);
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drm_plane_cleanup(plane);
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}
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static const struct drm_plane_funcs arc_pgu_plane_funcs = {
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.update_plane = drm_atomic_helper_update_plane,
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.disable_plane = drm_atomic_helper_disable_plane,
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.destroy = arc_pgu_plane_destroy,
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.reset = drm_atomic_helper_plane_reset,
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.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
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};
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static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm)
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{
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struct arcpgu_drm_private *arcpgu = drm->dev_private;
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struct drm_plane *plane = NULL;
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u32 formats[ARRAY_SIZE(supported_formats)], i;
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int ret;
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plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
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if (!plane)
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return ERR_PTR(-ENOMEM);
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for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
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formats[i] = supported_formats[i].fourcc;
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ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
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formats, ARRAY_SIZE(formats),
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NULL,
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DRM_PLANE_TYPE_PRIMARY, NULL);
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if (ret)
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return ERR_PTR(ret);
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drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
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arcpgu->plane = plane;
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return plane;
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}
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int arc_pgu_setup_crtc(struct drm_device *drm)
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{
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struct arcpgu_drm_private *arcpgu = drm->dev_private;
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struct drm_plane *primary;
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int ret;
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primary = arc_pgu_plane_init(drm);
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if (IS_ERR(primary))
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return PTR_ERR(primary);
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ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
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&arc_pgu_crtc_funcs, NULL);
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if (ret) {
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arc_pgu_plane_destroy(primary);
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return ret;
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}
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drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
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return 0;
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}
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