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303 lines
8.1 KiB
303 lines
8.1 KiB
/*
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* Copyright (C) 2016 Samsung Electronics. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#ifndef _ET5XX_LINUX_DIRVER_H_
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#define _ET5XX_LINUX_DIRVER_H_
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#include <linux/module.h>
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#include <linux/spi/spi.h>
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#include <linux/wakelock.h>
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#include <linux/regulator/consumer.h>
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#ifdef ENABLE_SENSORS_FPRINT_SECURE
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spidev.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#include <linux/msm-bus.h>
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#include <linux/msm-bus-board.h>
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#endif
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#include <linux/cpufreq.h>
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#include <linux/pinctrl/consumer.h>
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#include "../pinctrl/core.h"
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#include <linux/pm_qos.h>
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#ifdef ENABLE_SENSORS_FPRINT_SECURE
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#define FP_DDR_FREQ_CONTROL
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#endif
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#ifdef FP_DDR_FREQ_CONTROL
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#define MHZ_TO_BPS(mhz, w) ((uint64_t)mhz * 1000 * 1000 * w)
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#define NUM_BUS_TABLE 11
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#define BUS_W 4 /* SDM845 DDR Voting('w' for DDR is 4) */
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enum {
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MHZ_NONE = 0,
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MHZ_200,
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MHZ_300,
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MHZ_451,
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MHZ_547,
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MHZ_681,
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MHZ_768,
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MHZ_1017,
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MHZ_1296,
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MHZ_1555,
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MHZ_1803
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};
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static int ab_ib_bus_vectors[NUM_BUS_TABLE][2] = {
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{0, 0}, /* 0 */
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{0, 200}, /* 1 */
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{0, 300}, /* 2 */
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{0, 451}, /* 3 */
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{0, 547}, /* 4 */
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{0, 681}, /* 5 */
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{0, 768}, /* 6 */
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{0, 1017}, /* 7 */
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{0, 1296}, /* 8 */
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{0, 1555}, /* 9 */
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{0, 1803} /* 10 */
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};
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static u32 bus_hdl;
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static struct msm_bus_vectors fpsensor_reg_bus_vectors[NUM_BUS_TABLE];
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static struct msm_bus_paths fpsensor_reg_bus_usecases[ARRAY_SIZE(
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fpsensor_reg_bus_vectors)];
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static struct msm_bus_scale_pdata fpsensor_reg_bus_scale_table = {
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.usecase = fpsensor_reg_bus_usecases,
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.num_usecases = ARRAY_SIZE(fpsensor_reg_bus_usecases),
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.name = "fpsensor_bw",
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};
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#endif
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/*#define ET5XX_SPI_DEBUG*/
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#ifdef ET5XX_SPI_DEBUG
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#define DEBUG_PRINT(fmt, args...) pr_err(fmt, ## args)
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#else
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#define DEBUG_PRINT(fmt, args...)
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#endif
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#define VENDOR "EGISTEC"
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#define CHIP_ID "ET5XX"
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/* assigned */
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#define ET5XX_MAJOR 152
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/* ... up to 256 */
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#define N_SPI_MINORS 32
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#define OP_REG_R 0x20
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#define OP_REG_R_C 0x22
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#define OP_REG_R_C_BW 0x23
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#define OP_REG_W 0x24
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#define OP_REG_W_C 0x26
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#define OP_REG_W_C_BW 0x27
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#define OP_NVM_ON_R 0x40
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#define OP_NVM_ON_W 0x42
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#define OP_NVM_RE 0x44
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#define OP_NVM_WE 0x46
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#define OP_NVM_OFF 0x48
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#define OP_IMG_R 0x50
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#define OP_NBM_R 0x52
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#define OP_VDM_R 0x60
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#define OP_VDM_W 0x62
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#define OP_CLB_R 0x64
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#define OP_CLB_W 0x66
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#define BITS_PER_WORD 8
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#define SLOW_BAUD_RATE 12500000
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#define DRDY_IRQ_ENABLE 1
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#define DRDY_IRQ_DISABLE 0
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#define ET5XX_INT_DETECTION_PERIOD 10
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#define ET5XX_DETECTION_THRESHOLD 10
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#define FP_REGISTER_READ 0x01
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#define FP_REGISTER_WRITE 0x02
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#define FP_GET_ONE_IMG 0x03
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#define FP_SENSOR_RESET 0x04
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#define FP_POWER_CONTROL 0x05
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#define FP_SET_SPI_CLOCK 0x06
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#define FP_RESET_SET 0x07
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#define FP_REGISTER_BREAD 0x20
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#define FP_REGISTER_BWRITE 0x21
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#define FP_REGISTER_MREAD 0x22
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#define FP_REGISTER_MWRITE 0x23
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#define FP_REGISTER_BREAD_BACKWARD 0x24
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#define FP_REGISTER_BWRITE_BACKWARD 0x25
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#define FP_VDM_READ 0x30
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#define FP_VDM_WRITE 0x31
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#define FP_NVM_READ 0X40
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#define FP_NVM_WRITE 0x41
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#define FP_NVM_OFF 0x42
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#define FP_NVM_WRITEEX 0x43
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#define FP_NBM_READ 0x44
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#define FP_CLB_READ 0x45
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#define FP_CLB_WRITE 0x46
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#ifdef ENABLE_SENSORS_FPRINT_SECURE
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#define FP_DISABLE_SPI_CLOCK 0x10
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#define FP_CPU_SPEEDUP 0x11
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#define FP_SET_SENSOR_TYPE 0x14
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/* Do not use ioctl number 0x15 */
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#define FP_SET_LOCKSCREEN 0x16
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#define FP_SET_WAKE_UP_SIGNAL 0x17
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#endif
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#define FP_POWER_CONTROL_ET5XX 0x18
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#define FP_SENSOR_ORIENT 0x19
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#define FP_SPI_VALUE 0x1a
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#define FP_IOCTL_RESERVED_01 0x1b
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#define FP_IOCTL_RESERVED_02 0x1c
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/* trigger signal initial routine */
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#define INT_TRIGGER_INIT 0xa4
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/* trigger signal close routine */
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#define INT_TRIGGER_CLOSE 0xa5
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/* read trigger status */
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#define INT_TRIGGER_READ 0xa6
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/* polling trigger status */
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#define INT_TRIGGER_POLLING 0xa7
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/* polling abort */
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#define INT_TRIGGER_ABORT 0xa8
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/* Sensor Registers */
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#define FDATA_ET5XX_ADDR 0x00
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#define FSTATUS_ET5XX_ADDR 0x01
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/* Detect Define */
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#define FRAME_READY_MASK 0x01
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#define SHIFT_BYTE_OF_IMAGE 0
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#define DIVISION_OF_IMAGE 4
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#define LARGE_SPI_TRANSFER_BUFFER 64
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#define MAX_NVM_LEN (32 * 2) /* NVM length in bytes (32 * 16 bits internally) */
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#define NVM_WRITE_LENGTH 4096
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#define DETECT_ADM 1
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struct egis_ioc_transfer {
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u8 *tx_buf;
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u8 *rx_buf;
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__u32 len;
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__u32 speed_hz;
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__u16 delay_usecs;
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__u8 bits_per_word;
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__u8 cs_change;
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__u8 opcode;
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__u8 pad[3];
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};
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#define EGIS_IOC_MAGIC 'k'
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#define EGIS_MSGSIZE(N) \
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((((N)*(sizeof(struct egis_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \
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? ((N)*(sizeof(struct egis_ioc_transfer))) : 0)
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#define EGIS_IOC_MESSAGE(N) _IOW(EGIS_IOC_MAGIC, 0, char[EGIS_MSGSIZE(N)])
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struct etspi_data {
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dev_t devt;
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spinlock_t spi_lock;
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struct spi_device *spi;
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struct list_head device_entry;
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/* buffer is NULL unless this device is open (users > 0) */
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struct mutex buf_lock;
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unsigned int users;
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u8 *buf;/* tx buffer for sensor register read/write */
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unsigned int bufsiz; /* MAX size of tx and rx buffer */
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unsigned int drdyPin; /* DRDY GPIO pin number */
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unsigned int sleepPin; /* Sleep GPIO pin number */
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unsigned int ldo_pin; /* Ldo GPIO pin number */
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unsigned int min_cpufreq_limit;
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const char *btp_vdd;
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struct regulator *regulator_3p3;
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unsigned int spi_cs; /* spi cs pin <temporary gpio setting> */
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unsigned int drdy_irq_flag; /* irq flag */
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bool ldo_onoff;
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/* For polling interrupt */
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int int_count;
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struct timer_list timer;
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struct work_struct work_debug;
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struct workqueue_struct *wq_dbg;
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struct timer_list dbg_timer;
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int sensortype;
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u32 spi_value;
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struct device *fp_device;
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int reset_count;
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int interrupt_count;
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#ifdef ENABLE_SENSORS_FPRINT_SECURE
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bool enabled_clk;
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bool isGpio_cfgDone;
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struct wake_lock fp_spi_lock;
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#endif
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struct wake_lock fp_signal_lock;
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bool tz_mode;
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int detect_period;
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int detect_threshold;
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bool finger_on;
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const char *chipid;
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bool ldo_enabled;
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unsigned int orient;
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struct pinctrl *p;
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struct pinctrl_state *pins_sleep;
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struct pinctrl_state *pins_idle;
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struct pm_qos_request pm_qos;
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};
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int etspi_io_burst_read_register(struct etspi_data *etspi,
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struct egis_ioc_transfer *ioc);
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int etspi_io_burst_read_register_backward(struct etspi_data *etspi,
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struct egis_ioc_transfer *ioc);
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int etspi_io_burst_write_register(struct etspi_data *etspi,
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struct egis_ioc_transfer *ioc);
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int etspi_io_burst_write_register_backward(struct etspi_data *etspi,
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struct egis_ioc_transfer *ioc);
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int etspi_io_read_register(struct etspi_data *etspi,
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u8 *addr, u8 *buf);
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int etspi_io_read_registerex(struct etspi_data *etspi,
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u8 *addr, u8 *buf, u32 len);
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int etspi_io_write_register(struct etspi_data *etspi,
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u8 *buf);
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int etspi_read_register(struct etspi_data *etspi,
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u8 addr, u8 *buf);
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int etspi_write_register(struct etspi_data *etspi,
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u8 addr, u8 buf);
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int etspi_io_nvm_read(struct etspi_data *etspi,
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struct egis_ioc_transfer *ioc);
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int etspi_io_nvm_write(struct etspi_data *etspi,
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struct egis_ioc_transfer *ioc);
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int etspi_io_nvm_writeex(struct etspi_data *etspi,
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struct egis_ioc_transfer *ioc);
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int etspi_io_nvm_off(struct etspi_data *etspi,
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struct egis_ioc_transfer *ioc);
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int etspi_io_vdm_read(struct etspi_data *etspi,
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struct egis_ioc_transfer *ioc);
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int etspi_io_vdm_write(struct etspi_data *etspi,
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struct egis_ioc_transfer *ioc);
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int etspi_io_get_frame(struct etspi_data *etspi, u8 *frame, u32 size);
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int etspi_io_nbm_read(struct etspi_data *etspi, struct egis_ioc_transfer *ioc);
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int etspi_io_clb_read(struct etspi_data *etspi, struct egis_ioc_transfer *ioc);
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int etspi_io_clb_write(struct etspi_data *etspi, struct egis_ioc_transfer *ioc);
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#endif
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