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298 lines
12 KiB
298 lines
12 KiB
/*
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* Copyright 2012 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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/*
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*
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* An API for allocating, configuring, and manipulating TRIO hardware
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* resources
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*/
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/*
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*
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* The TILE-Gx TRIO shim provides connections to external devices via
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* PCIe or other transaction IO standards. The gxio_trio_ API,
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* declared in <gxio/trio.h>, allows applications to allocate and
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* configure TRIO IO resources like DMA command rings, memory map
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* windows, and device interrupts. The following sections introduce
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* the various components of the API. We strongly recommend reading
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* the TRIO section of the IO Device Guide (UG404) before working with
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* this API.
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*
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* @section trio__ingress TRIO Ingress Hardware Resources
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*
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* The TRIO ingress hardware is responsible for examining incoming
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* PCIe or StreamIO packets and choosing a processing mechanism based
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* on the packets' bus address. The gxio_trio_ API can be used to
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* configure different handlers for different ranges of bus address
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* space. The user can configure "mapped memory" and "scatter queue"
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* regions to match incoming packets within 4kB-aligned ranges of bus
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* addresses. Each range specifies a different set of mapping
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* parameters to be applied when handling the ingress packet. The
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* following sections describe how to work with MapMem and scatter
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* queue regions.
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*
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* @subsection trio__mapmem TRIO MapMem Regions
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*
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* TRIO mapped memory (or MapMem) regions allow the user to map
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* incoming read and write requests directly to the application's
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* memory space. MapMem regions are allocated via
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* gxio_trio_alloc_memory_maps(). Given an integer MapMem number,
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* applications can use gxio_trio_init_memory_map() to specify the
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* range of bus addresses that will match the region and the range of
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* virtual addresses to which those packets will be applied.
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*
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* As with many other gxio APIs, the programmer must be sure to
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* register memory pages that will be used with MapMem regions. Pages
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* can be registered with TRIO by allocating an ASID (address space
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* identifier) and then using gxio_trio_register_page() to register up to
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* 16 pages with the hardware. The initialization functions for
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* resources that require registered memory (MapMem, scatter queues,
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* push DMA, and pull DMA) then take an 'asid' parameter in order to
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* configure which set of registered pages is used by each resource.
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*
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* @subsection trio__scatter_queue TRIO Scatter Queues
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*
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* The TRIO shim's scatter queue regions allow users to dynamically
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* map buffers from a large address space into a small range of bus
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* addresses. This is particularly helpful for PCIe endpoint devices,
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* where the host generally limits the size of BARs to tens of
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* megabytes.
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*
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* Each scatter queue consists of a memory map region, a queue of
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* tile-side buffer VAs to be mapped to that region, and a bus-mapped
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* "doorbell" register that the remote endpoint can write to trigger a
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* dequeue of the current buffer VA, thus swapping in a new buffer.
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* The VAs pushed onto a scatter queue must be 4kB aligned, so
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* applications may need to use higher-level protocols to inform
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* remote entities that they should apply some additional, sub-4kB
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* offset when reading or writing the scatter queue region. For more
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* information, see the IO Device Guide (UG404).
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*
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* @section trio__egress TRIO Egress Hardware Resources
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*
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* The TRIO shim supports two mechanisms for egress packet generation:
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* programmed IO (PIO) and push/pull DMA. PIO allows applications to
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* create MMIO mappings for PCIe or StreamIO address space, such that
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* the application can generate word-sized read or write transactions
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* by issuing load or store instructions. Push and pull DMA are tuned
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* for larger transactions; they use specialized hardware engines to
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* transfer large blocks of data at line rate.
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*
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* @subsection trio__pio TRIO Programmed IO
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*
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* Programmed IO allows applications to create MMIO mappings for PCIe
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* or StreamIO address space. The hardware PIO regions support access
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* to PCIe configuration, IO, and memory space, but the gxio_trio API
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* only supports memory space accesses. PIO regions are allocated
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* with gxio_trio_alloc_pio_regions() and initialized via
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* gxio_trio_init_pio_region(). Once a region is bound to a range of
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* bus address via the initialization function, the application can
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* use gxio_trio_map_pio_region() to create MMIO mappings from its VA
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* space onto the range of bus addresses supported by the PIO region.
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*
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* @subsection trio_dma TRIO Push and Pull DMA
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*
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* The TRIO push and pull DMA engines allow users to copy blocks of
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* data between application memory and the bus. Push DMA generates
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* write packets that copy from application memory to the bus and pull
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* DMA generates read packets that copy from the bus into application
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* memory. The DMA engines are managed via an API that is very
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* similar to the mPIPE eDMA interface. For a detailed explanation of
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* the eDMA queue API, see @ref gxio_mpipe_wrappers.
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*
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* Push and pull DMA queues are allocated via
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* gxio_trio_alloc_push_dma_ring() / gxio_trio_alloc_pull_dma_ring().
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* Once allocated, users generally use a ::gxio_trio_dma_queue_t
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* object to manage the queue, providing easy wrappers for reserving
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* command slots in the DMA command ring, filling those slots, and
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* waiting for commands to complete. DMA queues can be initialized
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* via gxio_trio_init_push_dma_queue() or
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* gxio_trio_init_pull_dma_queue().
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*
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* See @ref trio/push_dma/app.c for an example of how to use push DMA.
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*
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* @section trio_shortcomings Plans for Future API Revisions
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*
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* The simulation framework is incomplete. Future features include:
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*
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* - Support for reset and deallocation of resources.
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*
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* - Support for pull DMA.
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*
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* - Support for interrupt regions and user-space interrupt delivery.
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*
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* - Support for getting BAR mappings and reserving regions of BAR
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* address space.
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*/
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#ifndef _GXIO_TRIO_H_
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#define _GXIO_TRIO_H_
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#include <linux/types.h>
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#include <gxio/common.h>
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#include <gxio/dma_queue.h>
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#include <arch/trio_constants.h>
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#include <arch/trio.h>
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#include <arch/trio_pcie_intfc.h>
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#include <arch/trio_pcie_rc.h>
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#include <arch/trio_shm.h>
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#include <hv/drv_trio_intf.h>
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#include <hv/iorpc.h>
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/* A context object used to manage TRIO hardware resources. */
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typedef struct {
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/* File descriptor for calling up to Linux (and thus the HV). */
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int fd;
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/* The VA at which the MAC MMIO registers are mapped. */
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char *mmio_base_mac;
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/* The VA at which the PIO config space are mapped for each PCIe MAC.
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Gx36 has max 3 PCIe MACs per TRIO shim. */
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char *mmio_base_pio_cfg[TILEGX_TRIO_PCIES];
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#ifdef USE_SHARED_PCIE_CONFIG_REGION
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/* Index of the shared PIO region for PCI config access. */
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int pio_cfg_index;
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#else
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/* Index of the PIO region for PCI config access per MAC. */
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int pio_cfg_index[TILEGX_TRIO_PCIES];
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#endif
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/* The VA at which the push DMA MMIO registers are mapped. */
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char *mmio_push_dma[TRIO_NUM_PUSH_DMA_RINGS];
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/* The VA at which the pull DMA MMIO registers are mapped. */
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char *mmio_pull_dma[TRIO_NUM_PUSH_DMA_RINGS];
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/* Application space ID. */
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unsigned int asid;
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} gxio_trio_context_t;
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/* Command descriptor for push or pull DMA. */
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typedef TRIO_DMA_DESC_t gxio_trio_dma_desc_t;
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/* A convenient, thread-safe interface to an eDMA ring. */
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typedef struct {
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/* State object for tracking head and tail pointers. */
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__gxio_dma_queue_t dma_queue;
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/* The ring entries. */
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gxio_trio_dma_desc_t *dma_descs;
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/* The number of entries minus one. */
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unsigned long mask_num_entries;
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/* The log2() of the number of entries. */
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unsigned int log2_num_entries;
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} gxio_trio_dma_queue_t;
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/* Initialize a TRIO context.
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*
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* This function allocates a TRIO "service domain" and maps the MMIO
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* registers into the the caller's VA space.
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*
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* @param trio_index Which TRIO shim; Gx36 must pass 0.
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* @param context Context object to be initialized.
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*/
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extern int gxio_trio_init(gxio_trio_context_t *context,
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unsigned int trio_index);
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/* This indicates that an ASID hasn't been allocated. */
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#define GXIO_ASID_NULL -1
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/* Ordering modes for map memory regions and scatter queue regions. */
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typedef enum gxio_trio_order_mode_e {
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/* Writes are not ordered. Reads always wait for previous writes. */
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GXIO_TRIO_ORDER_MODE_UNORDERED =
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TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_UNORDERED,
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/* Both writes and reads wait for previous transactions to complete. */
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GXIO_TRIO_ORDER_MODE_STRICT =
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TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_STRICT,
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/* Writes are ordered unless the incoming packet has the
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relaxed-ordering attributes set. */
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GXIO_TRIO_ORDER_MODE_OBEY_PACKET =
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TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_REL_ORD
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} gxio_trio_order_mode_t;
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/* Initialize a memory mapping region.
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*
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* @param context An initialized TRIO context.
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* @param map A Memory map region allocated by gxio_trio_alloc_memory_map().
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* @param target_mem VA of backing memory, should be registered via
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* gxio_trio_register_page() and aligned to 4kB.
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* @param target_size Length of the memory mapping, must be a multiple
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* of 4kB.
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* @param asid ASID to be used for Tile-side address translation.
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* @param mac MAC number.
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* @param bus_address Bus address at which the mapping starts.
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* @param order_mode Memory ordering mode for this mapping.
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* @return Zero on success, else ::GXIO_TRIO_ERR_BAD_MEMORY_MAP,
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* GXIO_TRIO_ERR_BAD_ASID, or ::GXIO_TRIO_ERR_BAD_BUS_RANGE.
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*/
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extern int gxio_trio_init_memory_map(gxio_trio_context_t *context,
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unsigned int map, void *target_mem,
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size_t target_size, unsigned int asid,
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unsigned int mac, uint64_t bus_address,
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gxio_trio_order_mode_t order_mode);
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/* Flags that can be passed to resource allocation functions. */
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enum gxio_trio_alloc_flags_e {
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GXIO_TRIO_ALLOC_FIXED = HV_TRIO_ALLOC_FIXED,
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};
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/* Flags that can be passed to memory registration functions. */
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enum gxio_trio_mem_flags_e {
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/* Do not fill L3 when writing, and invalidate lines upon egress. */
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GXIO_TRIO_MEM_FLAG_NT_HINT = IORPC_MEM_BUFFER_FLAG_NT_HINT,
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/* L3 cache fills should only populate IO cache ways. */
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GXIO_TRIO_MEM_FLAG_IO_PIN = IORPC_MEM_BUFFER_FLAG_IO_PIN,
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};
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/* Flag indicating a request generator uses a special traffic
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class. */
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#define GXIO_TRIO_FLAG_TRAFFIC_CLASS(N) HV_TRIO_FLAG_TC(N)
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/* Flag indicating a request generator uses a virtual function
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number. */
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#define GXIO_TRIO_FLAG_VFUNC(N) HV_TRIO_FLAG_VFUNC(N)
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/*****************************************************************
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* Memory Registration *
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******************************************************************/
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/* Allocate Application Space Identifiers (ASIDs). Each ASID can
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* register up to 16 page translations. ASIDs are used by memory map
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* regions, scatter queues, and DMA queues to translate application
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* VAs into memory system PAs.
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*
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* @param context An initialized TRIO context.
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* @param count Number of ASIDs required.
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* @param first Index of first ASID if ::GXIO_TRIO_ALLOC_FIXED flag
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* is set, otherwise ignored.
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* @param flags Flag bits, including bits from ::gxio_trio_alloc_flags_e.
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* @return Index of first ASID, or ::GXIO_TRIO_ERR_NO_ASID if allocation
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* failed.
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*/
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extern int gxio_trio_alloc_asids(gxio_trio_context_t *context,
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unsigned int count, unsigned int first,
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unsigned int flags);
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#endif /* ! _GXIO_TRIO_H_ */
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