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274 lines
6.2 KiB
274 lines
6.2 KiB
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_M32R_BITOPS_H
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#define _ASM_M32R_BITOPS_H
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/*
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* linux/include/asm-m32r/bitops.h
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*
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* Copyright 1992, Linus Torvalds.
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*
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* M32R version:
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* Copyright (C) 2001, 2002 Hitoshi Yamamoto
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* Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
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*/
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#ifndef _LINUX_BITOPS_H
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#error only <linux/bitops.h> can be included directly
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#endif
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#include <linux/compiler.h>
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#include <linux/irqflags.h>
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#include <asm/assembler.h>
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#include <asm/byteorder.h>
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#include <asm/dcache_clear.h>
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#include <asm/types.h>
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#include <asm/barrier.h>
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/*
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* These have to be done with inline assembly: that way the bit-setting
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* is guaranteed to be atomic. All bit operations return 0 if the bit
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* was cleared before the operation and != 0 if it was not.
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*
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* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
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*/
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static __inline__ void set_bit(int nr, volatile void * addr)
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{
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__u32 mask;
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volatile __u32 *a = addr;
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unsigned long flags;
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unsigned long tmp;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "r6", "%1")
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M32R_LOCK" %0, @%1; \n\t"
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"or %0, %2; \n\t"
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M32R_UNLOCK" %0, @%1; \n\t"
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: "=&r" (tmp)
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: "r" (a), "r" (mask)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r6"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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local_irq_restore(flags);
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}
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
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* in order to ensure changes are visible on other processors.
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*/
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static __inline__ void clear_bit(int nr, volatile void * addr)
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{
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__u32 mask;
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volatile __u32 *a = addr;
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unsigned long flags;
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unsigned long tmp;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "r6", "%1")
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M32R_LOCK" %0, @%1; \n\t"
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"and %0, %2; \n\t"
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M32R_UNLOCK" %0, @%1; \n\t"
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: "=&r" (tmp)
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: "r" (a), "r" (~mask)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r6"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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local_irq_restore(flags);
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}
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/**
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* change_bit - Toggle a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static __inline__ void change_bit(int nr, volatile void * addr)
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{
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__u32 mask;
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volatile __u32 *a = addr;
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unsigned long flags;
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unsigned long tmp;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "r6", "%1")
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M32R_LOCK" %0, @%1; \n\t"
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"xor %0, %2; \n\t"
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M32R_UNLOCK" %0, @%1; \n\t"
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: "=&r" (tmp)
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: "r" (a), "r" (mask)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r6"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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local_irq_restore(flags);
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}
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/**
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __inline__ int test_and_set_bit(int nr, volatile void * addr)
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{
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__u32 mask, oldbit;
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volatile __u32 *a = addr;
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unsigned long flags;
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unsigned long tmp;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "%1", "%2")
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M32R_LOCK" %0, @%2; \n\t"
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"mv %1, %0; \n\t"
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"and %0, %3; \n\t"
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"or %1, %3; \n\t"
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M32R_UNLOCK" %1, @%2; \n\t"
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: "=&r" (oldbit), "=&r" (tmp)
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: "r" (a), "r" (mask)
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: "memory"
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);
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local_irq_restore(flags);
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return (oldbit != 0);
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
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{
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__u32 mask, oldbit;
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volatile __u32 *a = addr;
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unsigned long flags;
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unsigned long tmp;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "%1", "%3")
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M32R_LOCK" %0, @%3; \n\t"
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"mv %1, %0; \n\t"
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"and %0, %2; \n\t"
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"not %2, %2; \n\t"
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"and %1, %2; \n\t"
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M32R_UNLOCK" %1, @%3; \n\t"
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: "=&r" (oldbit), "=&r" (tmp), "+r" (mask)
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: "r" (a)
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: "memory"
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);
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local_irq_restore(flags);
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return (oldbit != 0);
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}
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/**
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* test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __inline__ int test_and_change_bit(int nr, volatile void * addr)
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{
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__u32 mask, oldbit;
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volatile __u32 *a = addr;
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unsigned long flags;
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unsigned long tmp;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "%1", "%2")
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M32R_LOCK" %0, @%2; \n\t"
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"mv %1, %0; \n\t"
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"and %0, %3; \n\t"
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"xor %1, %3; \n\t"
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M32R_UNLOCK" %1, @%2; \n\t"
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: "=&r" (oldbit), "=&r" (tmp)
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: "r" (a), "r" (mask)
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: "memory"
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);
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local_irq_restore(flags);
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return (oldbit != 0);
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}
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#include <asm-generic/bitops/non-atomic.h>
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#include <asm-generic/bitops/ffz.h>
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#include <asm-generic/bitops/__ffs.h>
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#include <asm-generic/bitops/fls.h>
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#include <asm-generic/bitops/__fls.h>
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#include <asm-generic/bitops/fls64.h>
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#ifdef __KERNEL__
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/find.h>
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#include <asm-generic/bitops/ffs.h>
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#include <asm-generic/bitops/hweight.h>
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#include <asm-generic/bitops/lock.h>
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#endif /* __KERNEL__ */
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#ifdef __KERNEL__
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#include <asm-generic/bitops/le.h>
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#include <asm-generic/bitops/ext2-atomic.h>
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#endif /* __KERNEL__ */
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#endif /* _ASM_M32R_BITOPS_H */
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