Commit Graph

30 Commits (f5e902817fee1589badca1284f49eecc0ef0c200)

Author SHA1 Message Date
Atsushi Nemoto de862b488e [MIPS] TX49XX has prefetch. 19 years ago
Atsushi Nemoto de62893bc0 [MIPS] local_r4k_flush_cache_page fix 19 years ago
Ralf Baechle 4debe4f963 [MIPS] Initialize S-cache function pointers even on S-cache-less CPUs. 19 years ago
Atsushi Nemoto 41700e7399 [MIPS] Add protected_blast_icache_range, blast_icache_range, etc. 19 years ago
Atsushi Nemoto d4264f1839 [MIPS] Remove wrong __user tags. 19 years ago
Ralf Baechle e7958bb90d MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1. 19 years ago
Ralf Baechle 6ec25809c1 Rename page argument of flush_cache_page to something more descriptive. 19 years ago
Ralf Baechle 02cf211968 Cleanup the mess in cpu_cache_init. 19 years ago
Thiemo Seufer 10a3dabddd Add/Fix missing bit of R4600 hit cacheop workaround. 19 years ago
Thiemo Seufer 02fe2c9ce3 Minor code cleanup. 19 years ago
Thiemo Seufer d8748a3abf More .set push/pop. 19 years ago
Thiemo Seufer 330cfe016b Let r4600 PRID detection match only legacy CPUs, cleanups. 19 years ago
Ralf Baechle 1d40cfcd34 Avoid SMP cacheflushes. This is a minor optimization of startup but 19 years ago
Ralf Baechle e01402b115 More AP / SP bits for the 34K, the Malta bits and things. Still wants 19 years ago
Ralf Baechle ec74e361f1 Mark a few variables __read_mostly. 19 years ago
Ralf Baechle cc61c1fede MIPS R2 instruction hazard handling. 19 years ago
Thiemo Seufer ba5187dbb4 Better interface to run uncached cache setup code. 19 years ago
Ralf Baechle fe00f943e0 Sparseify MIPS. 19 years ago
Pete Popov e3ad1c23ba Base Au1200 2.6 support. 19 years ago
Thiemo Seufer 26a51b270f Use intermediate variable. 19 years ago
Ralf Baechle 79acf83e50 Moves a test which determines if we actually need to perform a 19 years ago
Ralf Baechle c6e8b58771 Update MIPS to use the 4-level pagetable code thereby getting rid of 19 years ago
Ralf Baechle 505403b6a0 25Kf is also physically indexed. 19 years ago
Ralf Baechle a95970f323 20Kc and SB1 don't suffer from aliases. 19 years ago
Ralf Baechle ae6aafe309 Move missplaced code line to the right place. 19 years ago
Ralf Baechle d1e344e500 Use hardware mechanism to deal with cache aliases in the 24K. 19 years ago
Ralf Baechle 28ecca4786 Remove old wrong bits of cache code. 19 years ago
Ralf Baechle 42a3b4f25a [PATCH] mips: nuke trailing whitespace 20 years ago
Ralf Baechle 875d43e72b [PATCH] mips: clean up 32/64-bit configuration 20 years ago
Linus Torvalds 1da177e4c3 Linux-2.6.12-rc2 20 years ago