Qualcomm's LLCC controller does not have an error IRQ line on lito and instead polls to check memory banks for errors every 5 seconds, which is inefficient and will add to system jitter. The generic Kryo CPU cache controller does have error IRQ lines so it doesn't need to use polling, but EDAC in general is fairly useless in its current state anyway because Google disabled the option to panic on uncorrectable error. Let's follow their decision and just disable EDAC entirely, as well as its placeholder RAS dependency. Signed-off-by: Danny Lin <danny@kdrag0n.dev> Signed-off-by: Alexander Winkowski <dereference23@outlook.com>fourteen
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