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97 lines
3.2 KiB
97 lines
3.2 KiB
20 years ago
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/*
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* A collection of structures, addresses, and values associated with
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* the Motorola MPC8260ADS/MPC8266ADS-PCI boards.
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* Copied from the RPX-Classic and SBS8260 stuff.
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*
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* Copyright (c) 2001 Dan Malek (dan@mvista.com)
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*/
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#ifdef __KERNEL__
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#ifndef __MACH_ADS8260_DEFS
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#define __MACH_ADS8260_DEFS
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#include <linux/config.h>
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#include <asm/ppcboot.h>
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/* Memory map is configured by the PROM startup.
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* We just map a few things we need. The CSR is actually 4 byte-wide
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* registers that can be accessed as 8-, 16-, or 32-bit values.
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*/
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#define CPM_MAP_ADDR ((uint)0xf0000000)
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#define BCSR_ADDR ((uint)0xf4500000)
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#define BCSR_SIZE ((uint)(32 * 1024))
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#define BOOTROM_RESTART_ADDR ((uint)0xff000104)
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/* For our show_cpuinfo hooks. */
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#define CPUINFO_VENDOR "Motorola"
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#define CPUINFO_MACHINE "PQ2 ADS PowerPC"
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/* The ADS8260 has 16, 32-bit wide control/status registers, accessed
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* only on word boundaries.
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* Not all are used (yet), or are interesting to us (yet).
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*/
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/* Things of interest in the CSR.
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*/
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#define BCSR0_LED0 ((uint)0x02000000) /* 0 == on */
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#define BCSR0_LED1 ((uint)0x01000000) /* 0 == on */
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#define BCSR1_FETHIEN ((uint)0x08000000) /* 0 == enable */
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#define BCSR1_FETH_RST ((uint)0x04000000) /* 0 == reset */
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#define BCSR1_RS232_EN1 ((uint)0x02000000) /* 0 == enable */
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#define BCSR1_RS232_EN2 ((uint)0x01000000) /* 0 == enable */
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#define BCSR3_FETHIEN2 ((uint)0x10000000) /* 0 == enable */
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#define BCSR3_FETH2_RST ((uint)0x80000000) /* 0 == reset */
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#define PHY_INTERRUPT SIU_INT_IRQ7
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#ifdef CONFIG_PCI
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/* PCI interrupt controller */
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#define PCI_INT_STAT_REG 0xF8200000
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#define PCI_INT_MASK_REG 0xF8200004
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#define PIRQA (NR_SIU_INTS + 0)
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#define PIRQB (NR_SIU_INTS + 1)
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#define PIRQC (NR_SIU_INTS + 2)
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#define PIRQD (NR_SIU_INTS + 3)
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/*
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* PCI memory map definitions for MPC8266ADS-PCI.
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*
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* processor view
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* local address PCI address target
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* 0x80000000-0x9FFFFFFF 0x80000000-0x9FFFFFFF PCI mem with prefetch
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* 0xA0000000-0xBFFFFFFF 0xA0000000-0xBFFFFFFF PCI mem w/o prefetch
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* 0xF4000000-0xF7FFFFFF 0x00000000-0x03FFFFFF PCI IO
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*
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* PCI master view
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* local address PCI address target
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* 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory
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*/
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/* window for a PCI master to access MPC8266 memory */
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#define PCI_SLV_MEM_LOCAL 0x00000000 /* Local base */
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#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
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/* window for the processor to access PCI memory with prefetching */
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#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
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#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
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#define PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
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/* window for the processor to access PCI memory without prefetching */
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#define PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
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#define PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
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#define PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
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/* window for the processor to access PCI I/O */
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#define PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
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#define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
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#define PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
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#define _IO_BASE PCI_MSTR_IO_LOCAL
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#define _ISA_MEM_BASE PCI_MSTR_MEMIO_LOCAL
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#define PCI_DRAM_OFFSET PCI_SLV_MEM_BUS
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#endif /* CONFIG_PCI */
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#endif /* __MACH_ADS8260_DEFS */
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#endif /* __KERNEL__ */
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