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/*
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* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
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*
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*/
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#ifndef _RTLX_H
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#define _RTLX_H_
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#define LX_NODE_BASE 10
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#define MIPSCPU_INT_BASE 16
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#define MIPS_CPU_RTLX_IRQ 0
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#define RTLX_VERSION 1
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#define RTLX_xID 0x12345600
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#define RTLX_ID (RTLX_xID | RTLX_VERSION)
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#define RTLX_CHANNELS 8
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#define RTLX_BUFFER_SIZE 1024
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/*
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* lx_state bits
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*/
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#define RTLX_STATE_OPENED 1UL
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/* each channel supports read and write.
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linux (vpe0) reads lx_buffer and writes rt_buffer
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SP (vpe1) reads rt_buffer and writes lx_buffer
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*/
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struct rtlx_channel {
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unsigned long lx_state;
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int buffer_size;
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/* read and write indexes per buffer */
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int rt_write, rt_read;
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char *rt_buffer;
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int lx_write, lx_read;
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char *lx_buffer;
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void *queues;
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};
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struct rtlx_info {
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unsigned long id;
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struct rtlx_channel channel[RTLX_CHANNELS];
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};
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#endif /* _RTLX_H_ */
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