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92 lines
3.3 KiB
92 lines
3.3 KiB
20 years ago
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/* megafunction wizard: %ARM-Based Excalibur%
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GENERATION: STANDARD
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VERSION: WM1.0
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MODULE: ARM-Based Excalibur
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PROJECT: excalibur
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============================================================
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File Name: v:\embedded\linux\bootldr\excalibur.h
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Megafunction Name(s): ARM-Based Excalibur
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============================================================
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************************************************************
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THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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************************************************************/
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#ifndef EXCALIBUR_H_INCLUDED
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#define EXCALIBUR_H_INCLUDED
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#define EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN
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#define EXC_DEFINE_BOOT_FROM_FLASH
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#define EXC_INPUT_CLK_FREQUENCY (50000000)
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#define EXC_AHB1_CLK_FREQUENCY (150000000)
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#define EXC_AHB2_CLK_FREQUENCY (75000000)
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#define EXC_SDRAM_CLK_FREQUENCY (75000000)
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/* Registers Block */
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#define EXC_REGISTERS_BASE (0x7fffc000)
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#define EXC_MODE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x000)
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#define EXC_IO_CTRL00_BASE (EXC_REGISTERS_BASE + 0x040)
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#define EXC_MMAP00_BASE (EXC_REGISTERS_BASE + 0x080)
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#define EXC_PLD_CONFIG00_BASE (EXC_REGISTERS_BASE + 0x140)
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#define EXC_TIMER00_BASE (EXC_REGISTERS_BASE + 0x200)
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#define EXC_INT_CTRL00_BASE (EXC_REGISTERS_BASE + 0xc00)
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#define EXC_CLOCK_CTRL00_BASE (EXC_REGISTERS_BASE + 0x300)
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#define EXC_WATCHDOG00_BASE (EXC_REGISTERS_BASE + 0xa00)
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#define EXC_UART00_BASE (EXC_REGISTERS_BASE + 0x280)
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#define EXC_EBI00_BASE (EXC_REGISTERS_BASE + 0x380)
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#define EXC_SDRAM00_BASE (EXC_REGISTERS_BASE + 0x400)
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#define EXC_AHB12_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x800)
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#define EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
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#define EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
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#define EXC_REGISTERS_SIZE (0x00004000)
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/* EBI Block(s) */
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#define EXC_EBI_BLOCK0_BASE (0x40000000)
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#define EXC_EBI_BLOCK0_SIZE (0x00400000)
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#define EXC_EBI_BLOCK0_WIDTH (8)
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#define EXC_EBI_BLOCK0_NON_CACHEABLE
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#define EXC_EBI_BLOCK1_BASE (0x40400000)
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#define EXC_EBI_BLOCK1_SIZE (0x00400000)
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#define EXC_EBI_BLOCK1_WIDTH (16)
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#define EXC_EBI_BLOCK1_NON_CACHEABLE
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#define EXC_EBI_BLOCK2_BASE (0x40800000)
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#define EXC_EBI_BLOCK2_SIZE (0x00400000)
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#define EXC_EBI_BLOCK2_WIDTH (16)
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#define EXC_EBI_BLOCK2_NON_CACHEABLE
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#define EXC_EBI_BLOCK3_BASE (0x40c00000)
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#define EXC_EBI_BLOCK3_SIZE (0x00400000)
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#define EXC_EBI_BLOCK3_WIDTH (16)
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#define EXC_EBI_BLOCK3_NON_CACHEABLE
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/* SDRAM Block(s) */
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#define EXC_SDRAM_BLOCK0_BASE (0x00000000)
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#define EXC_SDRAM_BLOCK0_SIZE (0x04000000)
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#define EXC_SDRAM_BLOCK0_WIDTH (32)
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#define EXC_SDRAM_BLOCK1_BASE (0x04000000)
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#define EXC_SDRAM_BLOCK1_SIZE (0x04000000)
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#define EXC_SDRAM_BLOCK1_WIDTH (32)
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/* Single Port SRAM Block(s) */
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#define EXC_SPSRAM_BLOCK0_BASE (0x08000000)
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#define EXC_SPSRAM_BLOCK0_SIZE (0x00020000)
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#define EXC_SPSRAM_BLOCK1_BASE (0x08020000)
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#define EXC_SPSRAM_BLOCK1_SIZE (0x00020000)
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/* PLD Block(s) */
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#define EXC_PLD_BLOCK0_BASE (0x80000000)
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#define EXC_PLD_BLOCK0_SIZE (0x00004000)
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#define EXC_PLD_BLOCK0_NON_CACHEABLE
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#define EXC_PLD_BLOCK1_BASE (0xf000000)
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#define EXC_PLD_BLOCK1_SIZE (0x00004000)
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#define EXC_PLD_BLOCK1_NON_CACHEABLE
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#define EXC_PLD_BLOCK2_BASE (0x80008000)
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#define EXC_PLD_BLOCK2_SIZE (0x00004000)
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#define EXC_PLD_BLOCK2_NON_CACHEABLE
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#define EXC_PLD_BLOCK3_BASE (0x8000c000)
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#define EXC_PLD_BLOCK3_SIZE (0x00004000)
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#define EXC_PLD_BLOCK3_NON_CACHEABLE
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#endif
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