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117 lines
3.6 KiB
117 lines
3.6 KiB
20 years ago
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/* gpio-regs.h: on-chip general purpose I/O registers
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*
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* Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_GPIO_REGS
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#define _ASM_GPIO_REGS
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#define __reg(ADDR) (*(volatile unsigned long *)(ADDR))
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#define __get_PDR() ({ __reg(0xfeff0400); })
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#define __set_PDR(V) do { __reg(0xfeff0400) = (V); mb(); } while(0)
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#define __get_GPDR() ({ __reg(0xfeff0408); })
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#define __set_GPDR(V) do { __reg(0xfeff0408) = (V); mb(); } while(0)
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#define __get_SIR() ({ __reg(0xfeff0410); })
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#define __set_SIR(V) do { __reg(0xfeff0410) = (V); mb(); } while(0)
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#define __get_SOR() ({ __reg(0xfeff0418); })
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#define __set_SOR(V) do { __reg(0xfeff0418) = (V); mb(); } while(0)
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#define __set_PDSR(V) do { __reg(0xfeff0420) = (V); mb(); } while(0)
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#define __set_PDCR(V) do { __reg(0xfeff0428) = (V); mb(); } while(0)
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#define __get_RSTR() ({ __reg(0xfeff0500); })
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#define __set_RSTR(V) do { __reg(0xfeff0500) = (V); mb(); } while(0)
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/* PDR definitions */
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#define PDR_GPIO_DATA(X) (1 << (X))
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/* GPDR definitions */
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#define GPDR_INPUT 0
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#define GPDR_OUTPUT 1
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#define GPDR_DREQ0_BIT 0x00001000
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#define GPDR_DREQ1_BIT 0x00008000
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#define GPDR_DREQ2_BIT 0x00040000
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#define GPDR_DREQ3_BIT 0x00080000
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#define GPDR_DREQ4_BIT 0x00004000
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#define GPDR_DREQ5_BIT 0x00020000
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#define GPDR_DREQ6_BIT 0x00100000
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#define GPDR_DREQ7_BIT 0x00200000
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#define GPDR_DACK0_BIT 0x00002000
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#define GPDR_DACK1_BIT 0x00010000
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#define GPDR_DACK2_BIT 0x00100000
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#define GPDR_DACK3_BIT 0x00200000
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#define GPDR_DONE0_BIT 0x00004000
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#define GPDR_DONE1_BIT 0x00020000
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#define GPDR_GPIO_DIR(X,D) ((D) << (X))
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/* SIR definitions */
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#define SIR_GPIO_INPUT 0
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#define SIR_DREQ7_INPUT 0x00200000
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#define SIR_DREQ6_INPUT 0x00100000
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#define SIR_DREQ3_INPUT 0x00080000
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#define SIR_DREQ2_INPUT 0x00040000
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#define SIR_DREQ5_INPUT 0x00020000
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#define SIR_DREQ1_INPUT 0x00008000
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#define SIR_DREQ4_INPUT 0x00004000
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#define SIR_DREQ0_INPUT 0x00001000
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#define SIR_RXD1_INPUT 0x00000400
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#define SIR_CTS0_INPUT 0x00000100
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#define SIR_RXD0_INPUT 0x00000040
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#define SIR_GATE1_INPUT 0x00000020
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#define SIR_GATE0_INPUT 0x00000010
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#define SIR_IRQ3_INPUT 0x00000008
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#define SIR_IRQ2_INPUT 0x00000004
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#define SIR_IRQ1_INPUT 0x00000002
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#define SIR_IRQ0_INPUT 0x00000001
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#define SIR_DREQ_BITS (SIR_DREQ0_INPUT | SIR_DREQ1_INPUT | \
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SIR_DREQ2_INPUT | SIR_DREQ3_INPUT | \
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SIR_DREQ4_INPUT | SIR_DREQ5_INPUT | \
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SIR_DREQ6_INPUT | SIR_DREQ7_INPUT)
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/* SOR definitions */
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#define SOR_GPIO_OUTPUT 0
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#define SOR_DACK3_OUTPUT 0x00200000
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#define SOR_DACK2_OUTPUT 0x00100000
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#define SOR_DONE1_OUTPUT 0x00020000
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#define SOR_DACK1_OUTPUT 0x00010000
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#define SOR_DONE0_OUTPUT 0x00004000
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#define SOR_DACK0_OUTPUT 0x00002000
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#define SOR_TXD1_OUTPUT 0x00000800
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#define SOR_RTS0_OUTPUT 0x00000200
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#define SOR_TXD0_OUTPUT 0x00000080
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#define SOR_TOUT1_OUTPUT 0x00000020
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#define SOR_TOUT0_OUTPUT 0x00000010
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#define SOR_DONE_BITS (SOR_DONE0_OUTPUT | SOR_DONE1_OUTPUT)
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#define SOR_DACK_BITS (SOR_DACK0_OUTPUT | SOR_DACK1_OUTPUT | \
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SOR_DACK2_OUTPUT | SOR_DACK3_OUTPUT)
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/* PDSR definitions */
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#define PDSR_UNCHANGED 0
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#define PDSR_SET_BIT(X) (1 << (X))
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/* PDCR definitions */
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#define PDCR_UNCHANGED 0
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#define PDCR_CLEAR_BIT(X) (1 << (X))
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/* RSTR definitions */
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/* Read Only */
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#define RSTR_POWERON 0x00000400
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#define RSTR_SOFTRESET_STATUS 0x00000100
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/* Write Only */
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#define RSTR_SOFTRESET 0x00000001
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#endif /* _ASM_GPIO_REGS */
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