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/*
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* File: include/asm-blackfin/mach-bf518/cdefbf514.h
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* Based on:
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* Author:
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*
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* Created:
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* Description: system mmr register map
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*
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* Rev:
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*
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* Modified:
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*
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _CDEF_BF514_H
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#define _CDEF_BF514_H
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/* include all Core registers and bit definitions */
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#include "defBF514.h"
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/* include core specific register pointer definitions */
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#include <asm/cdef_LPBlackfin.h>
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/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
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/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
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#include "cdefBF51x_base.h"
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/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
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/* Removable Storage Interface Registers */
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#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
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#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
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#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
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#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
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#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
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#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
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#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
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#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
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#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
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#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
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#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
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#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
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#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
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#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
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#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
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#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
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#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
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#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
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#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
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#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
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#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
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#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
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#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
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#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
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#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
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#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
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#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
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#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
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#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
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#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
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#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
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#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
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#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
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#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
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#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
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#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
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#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
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#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
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#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
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#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
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#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
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#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
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#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
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#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
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#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
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#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
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#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
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#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
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#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
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#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
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#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
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#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
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#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
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#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
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#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
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#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
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#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
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#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
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#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
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#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
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#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
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#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
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#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
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#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
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#endif /* _CDEF_BF514_H */
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