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79 lines
3.6 KiB
79 lines
3.6 KiB
14 years ago
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/*
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* arch/arm/mach-vt8500/include/mach/wm8505_regs.h
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*
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* Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_ARCH_WM8505_REGS_H
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#define __ASM_ARM_ARCH_WM8505_REGS_H
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/* WM8505 Registers Map */
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#define WM8505_REGS_START_PHYS 0xd8000000 /* Start of MMIO registers */
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#define WM8505_REGS_START_VIRT 0xf8000000 /* Virtual mapping start */
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#define WM8505_DDR_BASE 0xd8000400 /* 1k DDR/DDR2 Memory
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Controller */
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#define WM8505_DMA_BASE 0xd8001800 /* 1k DMA Controller */
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#define WM8505_VDMA_BASE 0xd8001c00 /* 1k VDMA */
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#define WM8505_SFLASH_BASE 0xd8002000 /* 1k Serial Flash Memory
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Controller */
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#define WM8505_ETHER_BASE 0xd8004000 /* 1k Ethernet MAC 0 */
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#define WM8505_CIPHER_BASE 0xd8006000 /* 4k Cipher */
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#define WM8505_USB_BASE 0xd8007000 /* 2k USB 2.0 Host */
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# define WM8505_EHCI_BASE 0xd8007100 /* EHCI */
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# define WM8505_UHCI_BASE 0xd8007301 /* UHCI */
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#define WM8505_PS2_BASE 0xd8008800 /* 1k PS/2 */
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#define WM8505_NAND_BASE 0xd8009000 /* 1k NAND Controller */
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#define WM8505_NOR_BASE 0xd8009400 /* 1k NOR Controller */
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#define WM8505_SDMMC_BASE 0xd800a000 /* 1k SD/MMC Controller */
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#define WM8505_VPU_BASE 0xd8050000 /* 256 VPU */
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#define WM8505_GOV_BASE 0xd8050300 /* 256 GOV */
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#define WM8505_GEGEA_BASE 0xd8050400 /* 768 GE/GE Alpha Mixing */
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#define WM8505_GOVR_BASE 0xd8050800 /* 512 GOVR (frambuffer) */
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#define WM8505_VID_BASE 0xd8050a00 /* 256 VID */
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#define WM8505_SCL_BASE 0xd8050d00 /* 256 SCL */
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#define WM8505_VPP_BASE 0xd8050f00 /* 256 VPP */
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#define WM8505_JPEGDEC_BASE 0xd80fe000 /* 4k JPEG Decoder */
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#define WM8505_RTC_BASE 0xd8100000 /* 64k RTC */
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#define WM8505_GPIO_BASE 0xd8110000 /* 64k GPIO Configuration */
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#define WM8505_SCC_BASE 0xd8120000 /* 64k System Configuration*/
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#define WM8505_PMC_BASE 0xd8130000 /* 64k PMC Configuration */
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#define WM8505_IC_BASE 0xd8140000 /* 64k Interrupt Controller*/
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#define WM8505_SIC_BASE 0xd8150000 /* 64k Secondary IC */
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#define WM8505_UART0_BASE 0xd8200000 /* 64k UART 0 */
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#define WM8505_UART2_BASE 0xd8210000 /* 64k UART 2 */
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#define WM8505_PWM_BASE 0xd8220000 /* 64k PWM Configuration */
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#define WM8505_SPI0_BASE 0xd8240000 /* 64k SPI 0 */
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#define WM8505_SPI1_BASE 0xd8250000 /* 64k SPI 1 */
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#define WM8505_KEYPAD_BASE 0xd8260000 /* 64k Keypad control */
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#define WM8505_CIR_BASE 0xd8270000 /* 64k CIR */
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#define WM8505_I2C0_BASE 0xd8280000 /* 64k I2C 0 */
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#define WM8505_AC97_BASE 0xd8290000 /* 64k AC97 */
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#define WM8505_SPI2_BASE 0xd82a0000 /* 64k SPI 2 */
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#define WM8505_UART1_BASE 0xd82b0000 /* 64k UART 1 */
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#define WM8505_UART3_BASE 0xd82c0000 /* 64k UART 3 */
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#define WM8505_I2C1_BASE 0xd8320000 /* 64k I2C 1 */
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#define WM8505_I2S_BASE 0xd8330000 /* 64k I2S */
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#define WM8505_UART4_BASE 0xd8370000 /* 64k UART 4 */
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#define WM8505_UART5_BASE 0xd8380000 /* 64k UART 5 */
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#define WM8505_REGS_END_PHYS 0xd838ffff /* End of MMIO registers */
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#define WM8505_REGS_LENGTH (WM8505_REGS_END_PHYS \
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- WM8505_REGS_START_PHYS + 1)
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#endif
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