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kernel_samsung_sm7125/include/linux/clkdev.h

62 lines
1.6 KiB

/*
* include/linux/clkdev.h
*
* Copyright (C) 2008 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Helper for the clk API to assist looking up a struct clk.
*/
#ifndef __CLKDEV_H
#define __CLKDEV_H
#include <asm/clkdev.h>
struct clk;
struct clk_hw;
struct device;
struct clk_lookup {
struct list_head node;
const char *dev_id;
const char *con_id;
clk: msm: Add snapshot of clock framework files This is snapshot of the clock framework files as of msm-4.9 'commit cc7a1542d987 ("msm: ipa: Fix assignment warning with clang"). Below is the brief description of the additional changes made: 1. Add COMMON_CLK_MSM config flag for conditional compilation for some common files used between COMMON_CLK_MSM and COMMON_CLK_QCOM clock framework files. 2. Add reset controller framework files for BCR operation. 3. Add conditional compilation support for FTRACE clock functions to maintain compatibility for clock framework based on COMMON_CLK_MSM and COMMON_CLK_QCOM. 4. Add files for GDSC operation. 5. Add BCR reset maps. 6. Resolve compilation issue for qti-quin-gvm. Some PLL HWs require an additional delay for the PLL lock detect to stabilize after being brought out of reset and SW to poll for lock detect status. Add delay of 50uSec before polling lock_det bit by introducing new pll ops. Also if PLL fails to lock, record additional PLL debug information in the kernel log before panic(). 'commit 90cb5ecd7cfd ("clk: msm: Add delay of 50uSec before polling lock_detect status")'. 1:1 is the MN divider preference for DSI PCLK for the regular 24 bpp use-case for display as per hardware recommendation. Update the divider array to give first priority to 1:1 divider combination. 'commit a270c07a1e21 ("clk: msm: update the fractional divider array for DSI PCLK")'. For some PLLs, there could be need to configure the calibration L value for auto calibration which PLL would use whenever it will come out of reset. Add support for the same by writing into USER_CTL_HI register. 'commit 05bd8759e347 ("clk: msm: Add support to configure calibration L value")'. Change-Id: I4260a9807e5e1b116db8f43fb9cfbbb55a5a8d67 Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Suresh Kumar Allam <allamsuresh@codeaurora.org>
5 years ago
int of_idx;
struct clk *clk;
struct clk_hw *clk_hw;
};
#define CLKDEV_INIT(d, n, c) \
{ \
.dev_id = d, \
.con_id = n, \
.clk = c, \
}
struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
const char *dev_fmt, ...) __printf(3, 4);
struct clk_lookup *clkdev_hw_alloc(struct clk_hw *hw, const char *con_id,
const char *dev_fmt, ...) __printf(3, 4);
void clkdev_add(struct clk_lookup *cl);
void clkdev_drop(struct clk_lookup *cl);
struct clk_lookup *clkdev_create(struct clk *clk, const char *con_id,
const char *dev_fmt, ...) __printf(3, 4);
struct clk_lookup *clkdev_hw_create(struct clk_hw *hw, const char *con_id,
const char *dev_fmt, ...) __printf(3, 4);
void clkdev_add_table(struct clk_lookup *, size_t);
int clk_add_alias(const char *, const char *, const char *, struct device *);
int clk_register_clkdev(struct clk *, const char *, const char *);
int clk_hw_register_clkdev(struct clk_hw *, const char *, const char *);
#ifdef CONFIG_COMMON_CLK
int __clk_get(struct clk *clk);
void __clk_put(struct clk *clk);
#endif
#endif