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231 lines
6.8 KiB
231 lines
6.8 KiB
/*
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*
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* Copyright 2010 Samsung Electronics S.LSI Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License")
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* @file csc_tiled_to_linear_y.s
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* @brief SEC_OMX specific define. It support MFC 6.x tiled.
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* @author ShinWon Lee (shinwon.lee@samsung.com)
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* @version 1.0
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* @history
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* 2011.12.01 : Create
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*/
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/*
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* Converts tiled data to linear for mfc 6.x
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* 1. Y of NV12T to Y of YUV420P
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* 2. Y of NV12T to Y of YUV420S
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*
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* @param dst
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* Y address of YUV420[out]
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*
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* @param src
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* Y address of NV12T[in]
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*
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* @param yuv420_width
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* real width of YUV420[in]. It should be even.
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*
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* @param yuv420_height
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* real height of YUV420[in] It should be even.
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*
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*/
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.arch armv7-a
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.text
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.global csc_tiled_to_linear_y_neon
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.type csc_tiled_to_linear_y_neon, %function
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csc_tiled_to_linear_y_neon:
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.fnstart
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.equ CACHE_LINE_SIZE, 64
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@r0 y_dst
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@r1 y_src
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@r2 width
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@r3 height
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@r4 temp3
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@r5 i
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@r6 j
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@r7 dst_offset
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@r8 src_offset
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@r9 aligned_height
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@r10 aligned_width
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@r11 tiled_width
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@r12 temp1
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@r14 temp2
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stmfd sp!, {r4-r12,r14} @ backup registers
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ldr r4, [sp, #40] @ r4 = height
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bic r9, r3, #0xF @ aligned_height = height & (~0xF)
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bic r10, r2, #0xF @ aligned_width = width & (~0xF)
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add r11, r2, #15 @ tiled_width = ((width + 15) >> 4) << 4
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mov r11, r11, asr #4
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mov r11, r11, lsl #4
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mov r5, #0
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LOOP_MAIN_ALIGNED_HEIGHT:
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mul r8, r11, r5 @ src_offset = tiled_width * i
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mov r6, #0
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add r8, r1, r8 @ src_offset = y_src + src_offset
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LOOP_MAIN_ALIGNED_WIDTH:
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pld [r8, #CACHE_LINE_SIZE]
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vld1.8 {q0, q1}, [r8]!
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vld1.8 {q2, q3}, [r8]!
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pld [r8, #CACHE_LINE_SIZE]
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vld1.8 {q4, q5}, [r8]!
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vld1.8 {q6, q7}, [r8]!
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mul r12, r2, r5 @ temp1 = width * i + j;
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pld [r8, #CACHE_LINE_SIZE]
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vld1.8 {q8, q9}, [r8]!
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add r12, r12, r6
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vld1.8 {q10, q11}, [r8]!
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add r7, r0, r12 @ dst_offset = y_dst + temp1
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pld [r8, #CACHE_LINE_SIZE]
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vld1.8 {q12, q13}, [r8]!
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vld1.8 {q14, q15}, [r8]!
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vst1.8 {q0}, [r7], r2
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vst1.8 {q1}, [r7], r2
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vst1.8 {q2}, [r7], r2
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vst1.8 {q3}, [r7], r2
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vst1.8 {q4}, [r7], r2
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vst1.8 {q5}, [r7], r2
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vst1.8 {q6}, [r7], r2
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vst1.8 {q7}, [r7], r2
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vst1.8 {q8}, [r7], r2
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vst1.8 {q9}, [r7], r2
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vst1.8 {q10}, [r7], r2
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vst1.8 {q11}, [r7], r2
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vst1.8 {q12}, [r7], r2
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vst1.8 {q13}, [r7], r2
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add r6, r6, #16
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vst1.8 {q14}, [r7], r2
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cmp r6, r10
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vst1.8 {q15}, [r7], r2
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blt LOOP_MAIN_ALIGNED_WIDTH
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MAIN_REMAIN_WIDTH_START:
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cmp r10, r2 @ if (aligned_width != width) {
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beq MAIN_REMAIN_WIDTH_END
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mul r8, r11, r5 @ src_offset = (tiled_width * i) + (j << 4);
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add r8, r8, r6, lsl #4
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add r8, r1, r8 @ r8 = y_src + src_offset
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mul r12, r2, r5 @ temp1 = width * i + j;
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add r12, r12, r6
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add r7, r0, r12 @ r7 = y_dst + temp1
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sub r14, r2, r6 @ r14 = width - j
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stmfd sp!, {r0-r1} @ backup registers
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mov r1, #0
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LOOP_MAIN_REMAIN_HEIGHT:
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mov r0, #0 @ r0 is index in memcpy
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LOOP_MAIN_REMAIN_WIDTH:
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ldrh r4, [r8], #2
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strh r4, [r7], #2
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add r0, #2
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cmp r0, r14
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blt LOOP_MAIN_REMAIN_WIDTH
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sub r8, r8, r14
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sub r7, r7, r14
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add r8, r8, #16
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add r7, r7, r2
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add r1, #1
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cmp r1, #16
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blt LOOP_MAIN_REMAIN_HEIGHT
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ldmfd sp!, {r0-r1} @ restore registers
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MAIN_REMAIN_WIDTH_END:
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add r5, r5, #16
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cmp r5, r9
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blt LOOP_MAIN_ALIGNED_HEIGHT
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REMAIN_HEIGHT_START:
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cmp r9, r3 @ if (aligned_height != height) {
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beq REMAIN_HEIGHT_END
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mov r6, #0
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LOOP_REMAIN_HEIGHT_WIDTH16:
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mul r8, r11, r5 @ src_offset = (tiled_width * i) + (j << 4)
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add r8, r8, r6, lsl #4
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add r8, r1, r8 @ src_offset = y_src + src_offset
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mul r12, r2, r5 @ temp1 = width * i + j;
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add r12, r12, r6
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add r7, r0, r12 @ r7 = y_dst + temp1
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sub r12, r3, r9
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mov r14, #0
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LOOP_REMAIN_HEIGHT_WIDTH16_HEIGHT1:
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vld1.8 {q0}, [r8]!
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vld1.8 {q1}, [r8]!
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vst1.8 {q0}, [r7], r2
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vst1.8 {q1}, [r7], r2
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add r14, r14, #2
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cmp r14, r12
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blt LOOP_REMAIN_HEIGHT_WIDTH16_HEIGHT1
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add r6, r6, #16
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cmp r6, r10
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blt LOOP_REMAIN_HEIGHT_WIDTH16
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REMAIN_HEIGHT_REMAIN_WIDTH_START:
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cmp r10, r2
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beq REMAIN_HEIGHT_REMAIN_WIDTH_END
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mul r8, r11, r5 @ src_offset = (tiled_width * i) + (j << 4)
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add r8, r8, r6, lsl #4
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add r8, r1, r8 @ src_offset = y_src + src_offset
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mul r12, r2, r5 @ temp1 = width * i + j;
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add r12, r12, r6
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add r7, r0, r12 @ r7 = y_dst + temp1
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stmfd sp!, {r0-r1,r3} @ backup registers
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mov r0, #0
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sub r1, r3, r9
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LOOP_REMAIN_HEIGHT_REMAIN_WIDTH_HEIGHT1:
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sub r14, r2, r6
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mov r4, #0
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LOOP_REMAIN_HEIGHT_REMAIN_WIDTH_HEIGHT1_WIDTHx:
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ldrh r3, [r8], #2
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strh r3, [r7], #2
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add r4, #2
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cmp r4, r14
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blt LOOP_REMAIN_HEIGHT_REMAIN_WIDTH_HEIGHT1_WIDTHx
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sub r8, r8, r14
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sub r7, r7, r14
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add r8, r8, #16
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add r7, r7, r2
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add r0, r0, #1
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cmp r0, r1
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blt LOOP_REMAIN_HEIGHT_REMAIN_WIDTH_HEIGHT1
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ldmfd sp!, {r0-r1,r3} @ restore registers
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REMAIN_HEIGHT_REMAIN_WIDTH_END:
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REMAIN_HEIGHT_END:
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RESTORE_REG:
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ldmfd sp!, {r4-r12,r15} @ restore registers
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.fnend
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