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134 lines
3.2 KiB
134 lines
3.2 KiB
12 years ago
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/*
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*
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* Copyright 2011 Samsung Electronics S.LSI Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* @file csc_interleave_memcpy.s
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* @brief SEC_OMX specific define
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* @author ShinWon Lee (shinwon.lee@samsung.com)
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* @version 1.0
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* @history
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* 2011.7.01 : Create
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*/
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.arch armv7-a
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.text
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.global csc_interleave_memcpy
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.type csc_interleave_memcpy, %function
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csc_interleave_memcpy:
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.fnstart
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@r0 dest
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@r1 src1
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@r2 src2
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@r3 src_size
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@r4 i
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@r5 temp1
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@r6 temp2
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@r7 temp3
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@r8 temp2
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@r9 temp3
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stmfd sp!, {r4-r12,r14} @ backup registers
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mov r4, #0
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cmp r3, #128
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blt LINEAR_SIZE_64
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bic r5, r3, #0x2F
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LINEAR_SIZE_128_LOOP:
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pld [r1, #64]
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vld1.8 {q0}, [r1]!
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vld1.8 {q2}, [r1]!
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vld1.8 {q4}, [r1]!
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vld1.8 {q6}, [r1]!
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pld [r2]
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vld1.8 {q8}, [r1]!
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vld1.8 {q10}, [r1]!
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vld1.8 {q12}, [r1]!
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vld1.8 {q14}, [r1]!
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pld [r2, #64]
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vld1.8 {q1}, [r2]!
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vld1.8 {q3}, [r2]!
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vld1.8 {q5}, [r2]!
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vld1.8 {q7}, [r2]!
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vld1.8 {q9}, [r2]!
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vld1.8 {q11}, [r2]!
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vld1.8 {q13}, [r2]!
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vld1.8 {q15}, [r2]!
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vst2.8 {q0, q1}, [r0]!
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vst2.8 {q2, q3}, [r0]!
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vst2.8 {q4, q5}, [r0]!
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vst2.8 {q6, q7}, [r0]!
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vst2.8 {q8, q9}, [r0]!
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vst2.8 {q10, q11}, [r0]!
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pld [r1]
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vst2.8 {q12, q13}, [r0]!
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vst2.8 {q14, q15}, [r0]!
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add r4, #128
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cmp r4, r5
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blt LINEAR_SIZE_128_LOOP
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LINEAR_SIZE_64:
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sub r5, r3, r4
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cmp r5, #64
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blt LINEAR_SIZE_2
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LINEAR_SIZE_64_LOOP:
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pld [r2]
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vld1.8 {q0}, [r1]!
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vld1.8 {q2}, [r1]!
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vld1.8 {q4}, [r1]!
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vld1.8 {q6}, [r1]!
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vld1.8 {q1}, [r2]!
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vld1.8 {q3}, [r2]!
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vld1.8 {q5}, [r2]!
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vld1.8 {q7}, [r2]!
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vst2.8 {q0, q1}, [r0]!
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vst2.8 {q2, q3}, [r0]!
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pld [r1]
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vst2.8 {q4, q5}, [r0]!
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vst2.8 {q6, q7}, [r0]!
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add r4, #64
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cmp r4, r3
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blt LINEAR_SIZE_64_LOOP
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LINEAR_SIZE_2:
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sub r5, r3, r4
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cmp r5, #2
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blt RESTORE_REG
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LINEAR_SIZE_2_LOOP:
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ldrb r6, [r1], #1
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ldrb r7, [r2], #1
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ldrb r8, [r1], #1
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ldrb r9, [r2], #1
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strb r6, [r0], #1
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strb r7, [r0], #1
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strb r8, [r0], #1
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strb r9, [r0], #1
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add r4, #2
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cmp r4, r3
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blt LINEAR_SIZE_2_LOOP
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RESTORE_REG:
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ldmfd sp!, {r4-r12,r15} @ restore registers
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.fnend
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